A semiconductor device 100 according to an embodiment including: a semiconductor element 2 placed on an insulating substrate 1 and having an electrode 21 on a surface 2a; a bonding wire 3 bonded to the electrode 21 and electrically coupling the semiconductor element 2; and a first resin material 4 covering a bonding portion 31 between the electrode 21 and the bonding wire 3, the bonding portion 31 includes a non-bonding region 32 where the electrode 21 and the bonding wire 3 are not bonded.

A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 m) and fifty micrometers (50 m) from the lead. In some embodiments, the core covers between at least approximately one-third () and one-half () of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core.

A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 m) and fifty micrometers (50 m) from the lead. In some embodiments, the core covers between at least approximately one-third () and one-half () of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core.

A semiconductor device includes a semiconductor layer, an electrode layer arranged on the semiconductor layer, a crack starting point layer arranged above the semiconductor layer, and a solder layer being in contact with the electrode layer and the crack starting point layer. A joining force between the solder layer and the crack starting point layer is smaller than a joining force between the solder layer and the electrode layer.

A customized seal ring for a semiconductor device is formed of multiple seal ring cells that are selected and arranged to produce a seal ring design. The cells include first cells that are coupled to ground and second cells that are not coupled to ground. The second cells that are not coupled to ground, include a higher density of metal features in an inner portion thereof, than the first seal ring cells. Dummy metal vias and other metal features that may be present in the inner portion of the second seal ring cells are absent from the inner portion of the first seal ring cells that are coupled to ground. The seal ring design may include various arrangements, including alternating and repeating sequences of the different seal ring cells.

A semiconductor structure, a package structure and a manufacturing method of a semiconductor structure are provided. The semiconductor structure includes a first semiconductor die, a second semiconductor die and an insulating encapsulant. The second semiconductor die is overlapped with and electrically connected to the first semiconductor die. The insulating encapsulant is disposed on the second semiconductor die and at least laterally encapsulates the first semiconductor die. The first semiconductor die includes a first portion and a second portion located between the first portion and the second semiconductor die. In a sectional view, the second portion is wider than the first portion.