A method for manufacturing an electronic circuit component includes: providing a first electronic component with one or several electrically conductive first contacts and with one or several insulating first supporting elements; providing a second electronic component with one or several electrically conductive second contacts and with one or several insulating second supporting elements; configuring a connecting structure with an interposer substrate, with electrically conductive third contacts, with one or several electrically conductive fourth contacts, with one or several insulating third supporting elements, with one or several electrically conductive fifth contacts, and with one or several insulating fourth supporting elements; connecting the first electronic component and the second electronic component to the connecting structure, wherein the first contacts are electrically connected to the fourth contacts, wherein the first supporting elements are mechanically connected to the third supporting elements, wherein the second contacts are electrically connected to the fifth contacts, and wherein the second supporting elements are mechanically connected to the fourth supporting elements, so that the first electronic component, the second electronic component, and the connecting structure are connected electrically and mechanically; removing a part of the interposer substrate so that the third contacts are exposed.

A display device including a display panel including a base layer, a circuit layer disposed on the base layer, and a pad part having a plurality of pads disposed on the base layer; and a driving chip disposed on the pad part and including a plurality of chip pads. The plurality of pads include a first pad having a smaller area than a corresponding chip pad among the plurality of chip pads and a second pad electrically connected to the circuit layer.

An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.

A 3D semiconductor device, the device including: a first die including first transistors and a first interconnect; a second die including second transistors and a second interconnect; and a third die including third transistors and a third interconnect, where the first die is overlaid by the second die, where the first die is overlaid by the third die, where the first die has a first die area and the second die has a second die area, where the first die area is at least 20% larger than the second die area, where the second die is pretested, where the second die is bonded to the first die, where the bonded includes metal to metal bonding, where the first die includes at least two first alignment marks positioned close to a first die edge of the first die, where the second die is aligned to the first die with less than 800 nm alignment error, where the second die includes at least two second alignment marks positioned close to a second die edge of the second die, and where the third die is bonded to the first die.

A method includes placing a first package component. The first package component includes a first alignment mark and a first dummy alignment mark. A second package component is aligned to the first package component. The second package component includes a second alignment mark and a second dummy alignment mark. The aligning is performed using the first alignment mark for positioning the first package component, and using the second alignment mark for position the second package component. The second package component is bonded to the first package component to form a package, with the first alignment mark being bonded to the second dummy alignment mark.

An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.

A semiconductor wafer, a bonding structure, and a wafer bonding method are provided. In the semiconductor wafer, a bonding pad which is electrically connected to the interconnection structure is formed in the top cover layer, and a bonding alignment mark formed by a point array is disposed in the top cover layer. In this way, the bonding alignment mark is disposed in the top cover layer, and the top cover layer is not covered by another material layer, thereby facilitating recognition of the alignment pattern by the bonding device and increasing the alignment window in bonding process. Moreover, the bonding alignment mark is formed by a point array, thereby facilitating integration of the process for forming the bonding alignment mark with the bonding hole process and avoiding defects such as the dishing phenomenon in the manufacturing process.

A semiconductor device has a plurality of first semiconductor die mounted over an interface layer formed over a temporary carrier. An encapsulant is deposited over the first die and carrier. A flat shielding layer is formed over the encapsulant. A channel is formed through the shielding layer and encapsulant down to the interface layer. A conductive material is deposited in the channel and electrically connected to the shielding layer. The interface layer and carrier are removed. An interconnect structure is formed over conductive material, encapsulant, and first die. The conductive material is electrically connected through the interconnect structure to a ground point. The conductive material is singulated to separate the first die. A second semiconductor die can be mounted over the first die such that the shielding layer covers the second die and the conductive material surrounds the second die or the first and second die.

An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.

An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.