A semiconductor device is provided that includes a dielectric layer, a bond pad, a passivation layer and a planar barrier. The bond pad is positioned in the dielectric layer. The passivation layer is positioned over the dielectric layer and has an opening over the bond pad. The planar barrier is positioned on the bond pad.

A semiconductor device is provided that includes a dielectric layer, a bond pad, a passivation layer and a planar barrier. The bond pad is positioned in the dielectric layer. The passivation layer is positioned over the dielectric layer and has an opening over the bond pad. The planar barrier is positioned on the bond pad.

In one embodiment, a method manufactures a semiconductor device including metallizations having peripheral portions with one or more underlying layers having marginal regions extending facing the peripheral portions. The method includes: providing a sacrificial layer to cover the marginal regions of the underlying layer, providing the metallizations while the marginal regions of the underlying layer are covered by the sacrificial layer, and removing the sacrificial layer so that the marginal regions of the underlying layer extend facing the peripheral portions in the absence of contact interface therebetween, thereby avoiding thermo-mechanical stresses.

A power semiconductor device, a power semiconductor module and a power semiconductor device processing method are provided. The power semiconductor device includes a first load terminal structure, a second load terminal structure, and a semiconductor structure electrically coupled to each load terminal structure and configured to carry a load current. The first load terminal structure includes a conductive layer in contact with the semiconductor structure, a bonding block configured to be contacted by at least one bond wire and to receive at least a part of the load current from the at least one bond wire and/or the conductive layer, a support block having a hardness greater than the hardness of the conductive layer and the bonding block. The bonding block is mounted on the conductive layer via the support block, and a zone is arranged within the conductive layer and/or the bonding block, the zone exhibiting nitrogen atoms.

A large scale integrated circuit chip includes a semiconductor circuit having a multilayered wiring structure, a metal guard ring surrounding the semiconductor circuit, and a plurality of external connection terminals, on a semiconductor circuit. The plurality of external connection terminals connect to an uppermost-layer wiring of the multilayered wiring structure and are exposed on a surface of the large scale integrated circuit chip. A predetermined external connection terminal conducts to a predetermined wiring through a conductive via within the guard ring and conducts to a conductive piece through another conductive via outside the guard ring. One side of the external connection terminal extending over the guard ring connects to the conductive piece, and the other side of the external connection terminal connects to the uppermost-layer wiring within the guard ring. Thus, a cutout part is not necessary in the guard ring.

A light-emitting device, a light-emitting assembly and an integrated circuit (IC) flip-chip are provided. The light-emitting device includes the IC flip-chip, a plurality of light-emitting diode (LED) flip-chips and a substrate. The IC flip-chip includes a plurality of flip-chip pads. The LED flip-chips are spaced apart from the IC flip-chip. The substrate carries the IC flip-chip and the LED flip-chips. The LED flip-chips have a plurality of electrodes, and the flip-chip pads of the IC flip-chip and the electrodes of the LED flip-chips are disposed on the substrate by way of soldering. The LED flip-chips are electrically coupled to the IC flip-chip through the substrate.

A light-emitting device, a light-emitting assembly and an integrated circuit (IC) flip-chip are provided. The light-emitting device includes the IC flip-chip, a plurality of light-emitting diode (LED) flip-chips and a substrate. The IC flip-chip includes a plurality of flip-chip pads. The LED flip-chips are spaced apart from the IC flip-chip. The substrate carries the IC flip-chip and the LED flip-chips. The LED flip-chips have a plurality of electrodes, and the flip-chip pads of the IC flip-chip and the electrodes of the LED flip-chips are disposed on the substrate by way of soldering. The LED flip-chips are electrically coupled to the IC flip-chip through the substrate.

A power module package is provided. The power module package may include: a first substrate; a second substrate; a semiconductor chip disposed between the first substrate and the second substrate; and a mutual-connection layer that is formed between the semiconductor chip and the second substrate and provides conductive connection between the semiconductor chip and the second substrate.

A power module package is provided. The power module package may include: a first substrate; a second substrate; a semiconductor chip disposed between the first substrate and the second substrate; and a mutual-connection layer that is formed between the semiconductor chip and the second substrate and provides conductive connection between the semiconductor chip and the second substrate.

In a semiconductor device, a first protection film covers an end portion of a first metal layer disposed on a semiconductor substrate, and has a first opening above the first metal layer. A second metal layer is disposed on the first metal layer in the first opening. An oxidation inhibition layer is disposed on the second metal layer in the first opening. A second protection film has a second opening and covers an end portion of the oxidation inhibition layer and the first protection film. The second protection film has an opening peripheral portion on a periphery of the second opening, and covers the end portion of the oxidation inhibition layer. An adhesion portion adheres to a portion of a lower surface of the opening peripheral portion. The adhesion portion has a higher adhesive strength with the second protection film than the oxidation inhibition layer.