A chip structure is provided. The chip structure includes a substrate, a redistribution layer over the substrate, a bonding pad over the redistribution layer, a shielding pad over the redistribution layer and surrounding the bonding pad, an insulating layer over the redistribution layer and the shielding pad, and a bump over the bonding pad and the insulating layer. The insulating layer includes a first part and a second part surrounded by the first part, the first part has first thickness, the second part has a second thickness, and the first thickness and the second thickness are different.

A package structure includes a die, an encapsulant, a dam structure, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The encapsulant encapsulates sidewalls of the die. The encapsulant has a first surface and a second surface opposite to the first surface. The first surface is coplanar with the rear surface of the die. The second surface is located at a level height different from the active surface of the die. The dam structure is disposed on the active surface of the die. A top surface of the dam structure is substantially coplanar with the second surface of the encapsulant. The redistribution structure is over the encapsulant, the dam structure, and the die. The redistribution structure is electrically connected to the die.

A semiconductor device includes a semiconductor chip having a passivation film, a stress relieving layer provided on the passivation film, and a groove formed in a periphery of a surface of the semiconductor chip, the groove being provided inside of an edge of the semiconductor chip, wherein the stress relieving layer is partly disposed in the groove.

A display device includes a substrate including a display region, and a peripheral region that is outside of the display region, a plurality of dummy pads at the peripheral region, an insulating layer covering the plurality of dummy pads, wherein top surfaces of first portions of the insulating layer above the plurality of dummy pads are higher than top surfaces of second portions of the insulating layer between the plurality of dummy pads, and a plurality of pads over the second portions of the insulating layer at the peripheral region.

A micro-connection structure is provided. The micro-connection structure includes an under bump metallurgy (UBM) pad, a bump and an insulating ring. The UBM pad is electrically connected to at least one metallic contact of a substrate. The bump is disposed on the UBM pad and electrically connected with the UBM pad. The insulating ring surrounds the bump and the UBM pad. The bump is separate from the insulating ring with a distance and the bump is isolated by a gap between the insulating ring and the bump.

CMOS sensors and methods of forming the same are disclosed. The CMOS sensor includes a semiconductor substrate, a plurality of dielectric patterns, a first conductive element and a second conductive element. The semiconductor substrate has a pixel region and a circuit region. The dielectric patterns are disposed between the first portion and the second portion, wherein top surfaces of the plurality of dielectric patterns are lower than top surfaces of the first and second portions. The first conductive element is disposed below the plurality of dielectric patterns. The second conductive element inserts between the plurality of dielectric patterns to electrically connect the first conductive element.

A semiconductor device (10) includes: a substrate (1); a wiring (6) formed above the substrate (1); a titanium nitride film (7) formed on the wiring (6); an oxide film (3) formed on the titanium nitride film (7); a silicon nitride film (4) formed on the oxide film (3); and a pad portion (8) exposing the wiring (6), and formed at a place where a first opening portion (91) formed in the silicon nitride film (4) and a second opening portion (92) formed in the titanium nitride film (7) overlap with each other in plan view, and being inside a third opening portion (93) formed in the oxide film (3) in plan view, wherein the silicon nitride film (4) is formed on top of and in contact with the titanium nitride film (7) inside the third opening portion (93) in plan view.

Packaging methods for semiconductor devices and methods of packaging thereof are disclosed. In some embodiments, a device includes a packaging apparatus and contact pads disposed on the packaging apparatus. The contact pads are arranged in an array of rows and columns. The contact pads include first contact pads proximate a perimeter region of the packaging apparatus and second contact pads disposed in an interior region of the packaging apparatus. A dam structure that is continuous is disposed around the second contact pads. The contact pads comprise a mounting region for a semiconductor device.

Bond pad structures and methods for fabricating bond pad structures. A bond pad and a plurality of fill lines are formed on the top surface of a dielectric layer. The fill lines are arranged on the top surface of the dielectric layer adjacent to the bond pad, and may be separated from the bond pad by a fill keep-out zone. One or more Under Bump Metallurgy (UBM) layers may be arranged on the bond pad and may extend outwardly to overlap with the fill lines.

A semiconductor device (10) includes: a substrate (1); a wiring (6) formed above the substrate (1); a titanium nitride film (7) formed on the wiring (6); an oxide film (3) formed on the titanium nitride film (7); a silicon nitride film (4) formed on the oxide film (3); and a pad portion (8) exposing the wiring (6), and formed at a place where a first opening portion (91) formed in the silicon nitride film (4) and a second opening portion (92) formed in the titanium nitride film (7) overlap with each other in plan view, and being inside a third opening portion (93) formed in the oxide film (3) in plan view, wherein the silicon nitride film (4) is formed on top of and in contact with the titanium nitride film (7) inside the third opening portion (93) in plan view.