In a described example, a method includes: forming a metal layer on a backside surface of a semiconductor wafer, the semiconductor wafer having semiconductor dies spaced apart by scribe lanes on an active surface of the semiconductor wafer opposite the backside surface; forming a layer with a modulus greater than about 4000 MPa up to about 8000 MPa over the metal layer; mounting the backside of the semiconductor wafer on a first side of a dicing tape having an adhesive; cutting through the semiconductor wafer, the metal layer, and the layer with a modulus greater than about 4000 MPa up to about 8000 MPa along scribe lanes; separating the semiconductor dies from the semiconductor wafer and from one another by stretching the dicing tape, expanding the cuts in the semiconductor wafer along the scribe lanes between the semiconductor dies; and removing the separated semiconductor dies from the dicing tape.

In a described example, a method includes: forming a metal layer on a backside surface of a semiconductor wafer, the semiconductor wafer having semiconductor dies spaced apart by scribe lanes on an active surface of the semiconductor wafer opposite the backside surface; forming a layer with a modulus greater than about 4000 MPa up to about 8000 MPa over the metal layer; mounting the backside of the semiconductor wafer on a first side of a dicing tape having an adhesive; cutting through the semiconductor wafer, the metal layer, and the layer with a modulus greater than about 4000 MPa up to about 8000 MPa along scribe lanes; separating the semiconductor dies from the semiconductor wafer and from one another by stretching the dicing tape, expanding the cuts in the semiconductor wafer along the scribe lanes between the semiconductor dies; and removing the separated semiconductor dies from the dicing tape.

The invention relates to a foil-based package having at least one foil substrate having an electrically conductive layer arranged thereon, at least one electronic device having a device terminal pad having at least one device terminal pad, and a plurality of package terminal pads arranged on a package terminal side. The foil substrate includes a first foil portion and a second foil portion, the first foil portion extending along a first foil plane and the second foil portion extending along a second foil plane parallel to the first foil plane, the first foil plane and the second foil plane being offset relative to each other so that the foil substrate forms a recess within which the at least one electronic device is arranged.

The present invention relates to a conductive paste for bonding that comprises a metal powder and a solvent, wherein the metal powder comprises a first metal powder having a particle diameter (D50) of 10 to 150 nm and a second metal powder having a particle diameter (D50) of 151 to 500 nm. The paste is useful for manufacturing an electronic device comprising a substrate with an electrically conductive layer and an electrical or electronic component, which are reliably bonded together using the paste.

The present invention relates to a conductive paste for bonding that comprises a metal powder and a solvent, wherein the metal powder comprises a first metal powder having a particle diameter (D50) of 10 to 150 nm and a second metal powder having a particle diameter (D50) of 151 to 500 nm. The paste is useful for manufacturing an electronic device comprising a substrate with an electrically conductive layer and an electrical or electronic component, which are reliably bonded together using the paste.

Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die.

Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die.

A semiconductor package includes a semiconductor chip having a first surface that is an active surface and a second surface opposing the first surface, a first redistribution portion disposed on the first surface, the first redistribution portion including a lower wiring layer electrically connected to the semiconductor chip, a thermal conductive layer disposed on the second surface of the semiconductor chip, a sealing layer surrounding a side surface of the semiconductor chip and a side surface of the thermal conductive layer, and a second redistribution portion disposed on the sealing layer, the second redistribution portion including a first upper wiring layer connected to the thermal conductive layer, the second redistribution portion including a second upper wiring layer electrically connected to the semiconductor chip.

A semiconductor package includes a semiconductor chip having a first surface that is an active surface and a second surface opposing the first surface, a first redistribution portion disposed on the first surface, the first redistribution portion including a lower wiring layer electrically connected to the semiconductor chip, a thermal conductive layer disposed on the second surface of the semiconductor chip, a sealing layer surrounding a side surface of the semiconductor chip and a side surface of the thermal conductive layer, and a second redistribution portion disposed on the sealing layer, the second redistribution portion including a first upper wiring layer connected to the thermal conductive layer, the second redistribution portion including a second upper wiring layer electrically connected to the semiconductor chip.

A surface electrode on the front surface of a semiconductor element and a metal foil provided on the surface electrode are partially joined, which makes it possible to reduce stress generated at the end of the metal foil, prevent a failure resulting from a crack in the front surface of the semiconductor element, and enhance reliability of the semiconductor device. Such a semiconductor device includes a semiconductor element having a front surface and a back surface, a surface electrode formed on the front surface of the semiconductor element, and a metal foil partially joined onto an upper surface of the surface electrode.