An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a thermally conductive flow layer underlying the sintered metallic layer, and a thermally conductive substrate underlying the thermally conductive flow layer.

Systems and methods are provided for the embedding of thin chips. A well region is generated in a substrate that includes a conductive material disposed on a flexible polymer. The standoff well region can be generated by pattern the conductive material, where the thin chip is embedded in the standoff well region. A cavity can be generated in the polymer layer to form a polymer well region, where the thin chip is embedded in the polymer well region.

Methods of fabricating integrated circuits are disclosed herein. A die having a side is provided. A conductive stud extends from the side in a direction that is substantially normal to the side. A first dielectric layer is affixed to the side of the die. The first dielectric layer has a first side and a second side. The first side of the first dielectric layer is affixed to the side of the die. The conductive stud pierces the first side of the first dielectric layer. A first via is formed through the first dielectric layer between the conductive stud and the second side. The first via is electrically connected to the conductive stud.

A package comprising a first substrate; a first integrated device coupled to the first substrate; an interconnection die coupled to the first substrate; a second substrate coupled to the first substrate through the interconnection die such that the first integrated device and the interconnection die are located between the first substrate and the second substrate; and an encapsulation layer coupled to the first substrate and the second substrate, wherein the encapsulation layer is located between the first substrate and the second substrate.