A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.

An element is disclosed. The element can include a non-conductive structure having a non-conductive bonding surface, a cavity at least partially extending through a portion of a thickness of the non-conductive structure from the non-conductive bonding surface, and a conductive pad disposed in the cavity. The cavity has a bottom side and a sidewall. The conductive pad has a bonding surface and a back side opposite the bonding surface. An average size of the grains at the bonding surface is smaller than an average size of the grains adjacent the bottom side of the cavity. The conductive pad can include a crystal structure with grains oriented along a 111 crystal plane. The element can be bonded to another element to form a bonded structure. The element and the other element can be directly bonded to one another without an intervening adhesive.

A semiconductor-chip stack package includes a plurality of semiconductor chips disposed in a stack arrangement and at least one connecting substrate which connects the semiconductor chips. The semiconductor chips include a chip terminal face on a chip edge extending at least partially as a side terminal face in a side surface of the semiconductor chip. The side surfaces of the semiconductor chips provided with the side terminal face are arranged in a shared side surface plane S of the semiconductor-chip stack arrangement. The connecting substrate is arranged with a contact surface parallel to the side surface plane S of the semiconductor chips. Substrate terminal faces are formed on the contact surface for connecting a connection conductor structure formed in the connecting substrate and which are connected to the side terminal faces via a connecting material in a connection plane V1 parallel to the contact surface.

A semiconductor package for high-speed die connections using a conductive insert, the semiconductor package comprising: a die; a plurality of redistribution layers; a conductive insert housed in a perforation through the plurality of redistribution layers; and a conductive bump conductively coupled to an input/output (I/O) connection point of the die via the conductive insert.

Provided are a chip packaging method and a chip packaging structure. A passivation layer is provided on a pad of a wafer, a first metal bonding layer is then formed on the passivation layer, a second metal bonding layer is formed on a substrate, the substrate and the wafer are bonded and packaged together through bonding of the first metal bonding layer and the second metal bonding layer, a first shielding layer is provided on the substrate, and the first shielding layer is connected to the second metal bonding layer; and after the wafer and the substrate are bonded, semi-cutting is performed on the wafer until the first metal bonding layer is exposed, and a second shielding layer is then formed, and the second shielding layer is electrically connected to the first metal bonding layer, such that an electromagnetic shielding structure jointly composed of the first shielding layer, the second metal bonding layer, the second shielding layer and the first metal bonding layer is obtained. The shielding structure is thus approximately closed, thereby improving the electromagnetic shielding effect.

The invention concerns a device comprising a support, an electrically-conductive layer covering the support, a semiconductor substrate on the conductive layer, and an insulating casing.

The invention concerns a device comprising a support, an electrically-conductive layer covering the support, a semiconductor substrate on the conductive layer, and an insulating casing.

Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is provided. The method includes the following operations. In a first semiconductor structure, a first bonding layer is formed having a first dielectric layer and a plurality of protruding contact structures. In a second semiconductor structure, a second bonding layer is formed having a second dielectric layer and a plurality of recess contact structures. The plurality of protruding contact structures are bonded with the plurality of recess contact structures such that each of the plurality of protruding contacts is in contact with a respective recess contact structure.

Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.

Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.