A semiconductor package includes a second semiconductor chip disposed on a first semiconductor chip. The first semiconductor chip includes a first semiconductor substrate, a through via, and a lower pad disposed on the through via. The lower pad includes a first segment and a second segment connected thereto. The first segment overlaps the through via. The second segment is disposed on an edge region of the first segment. The second segment has an annular shape. The second semiconductor chip includes a second semiconductor substrate, an upper pad disposed on a bottom surface of the second semiconductor substrate, and a connection terminal disposed between the upper and lower pads. The second segment at least partially surrounds a lateral surface of the upper pad. A level of a top surface of the second segment is higher than that of an uppermost portion of the connection terminal.

A display device includes a substrate including a plurality of emission areas respectively corresponding to a plurality of subpixels for displaying an image, a plurality of light emitting elements respectively located in the plurality of emission areas of a first surface of the substrate and respectively corresponding to the plurality of subpixels, a first planarization layer on the first surface of the substrate and covering the plurality of light emitting elements, and an array layer on the first planarization layer.

A semiconductor package may include a base, a first chip on the base, and first connection patterns that connect and couple the base and the first chip. The first chip may include a substrate, pad patterns on the substrate, a passivation layer on the substrate and having openings, and pillars on the substrate, the pad patterns include a first signal pad and a second signal pad, the first connection patterns are in contact with the pillars, the pillars include a first signal pillar in contact with the first signal pad and a second signal pillar in contact with the second signal pad, the openings in the passivation layer include a first opening having a sidewall facing a side surface of the first signal pillar and surrounding the side surface of the first signal pillar, and a second opening having a sidewall facing a side surface of the second signal pillar and surrounding the side surface of the second signal pillar, and a maximum width of the second opening is greater than a maximum width of the first opening.

In a semiconductor device, a first wiring member is electrically connected to a first main electrode on a first surface of a semiconductor element, and a second wiring member is electrically connected to a second main electrode on a second surface of the semiconductor element. An encapsulating body encapsulates at least a part of each of the first and second wiring members, the semiconductor element and a bonding wire. The semiconductor element has a protective film on the first surface of the semiconductor substrate, and the pad has an exposed surface exposed from an opening of the protective film. The exposed surface includes a connection area to which the bonding wire is connected, and a peripheral area on a periphery of the connection area. The peripheral area has a surface that defines an angle of 90 degrees or less relative to a surface of the connection area.

A semiconductor package includes: a first semiconductor chip; a second semiconductor chip; and a bonding structure at an interface between the first and second semiconductor chips. The bonding structure includes: a first bonding insulating layer on the first semiconductor chip; a first connection pad in a first pad opening formed in the first bonding insulating layer, the first connection pad including a first pad layer, a first interface layer including a copper oxide, and a first capping layer; a second bonding insulating layer on the second semiconductor chip; and a second connection pad in a second pad opening formed in the second bonding insulating layer, the second connection pad including a second pad layer, a second interface layer including a copper oxide, and a second capping layer. The first and second capping layers include copper monocrystal layers having a (111) orientation.

A display device includes a substrate including a pad area, a first conductive pattern disposed in the pad area on the substrate, an insulating layer disposed on the first conductive pattern and overlapping the first conductive pattern, second conductive patterns disposed on the insulating layer, spaced apart from each other, and contacting the first conductive pattern through contact holes formed in the insulating layer, and a third conductive pattern disposed on the second conductive patterns and contacting the insulating layer.

A light emitting device according to an embodiment of the present disclosure includes multiple light emitting elements. The light emitting elements each include a semiconductor layer including a first conductive layer, a light emitting layer, and a second conductive layer that are stacked in this order. The first conductive layer has a light emitting surface. The light emitting elements further includes a first electrode in contact with the second conductive layer, and a second electrode in contact with the first conductive layer. The light emitting elements share the first conductive layer and the second electrode with each other. The light emitting elements each include a current path in the first conductive layer from a portion opposed to the first electrode to a portion opposed to the second electrode. The first conductive layer has one or multiple trenches in a region between two current paths adjacent to each other. The light emitting device further includes a light blocking section provided in the one or multiple trenches.

The present disclosure relates to a display panel, a display device and a manufacturing method of a display panel. The display panel includes: a display substrate having a display area and a non-display area, the display substrate including a substrate and an IC bonding portion which includes: a pin; a first passivation layer located on one side of the substrate adjacent to the pin and covering a peripheral area of the pin, and exposing a central area of the pin; a first barrier layer located on one side of the first passivation layer away from the substrate and covered at the first passivation layer and an edge of the first passivation layer connected to the pin; and a first metal layer located on one side of the first barrier layer away from the substrate, at least covering a central portion of the pin, and electrically connected to the pin.

A semiconductor device, a semiconductor device package, and a method of manufacturing a semiconductor device package are provided. The semiconductor device includes an electronic component and a first protection layer. The electronic component includes a first conductive pad protruded out of a first surface of the electronic component. The first protection layer covers an external surface of the first conductive pad. The first surface of the electronic component is exposed from the first protection layer.

A driving backplane, a transfer method for a light-emitting diode chip (21), and a display apparatus. The driving backplane comprises: a base substrate (10), a driving circuit, a plurality of electromagnetic structures (13), and a plurality of contact electrodes (12). The plurality of electromagnetic structures (13) in the driving backplane are symmetrically arranged relative to a first straight line (L1) and a second straight line (L2). A current signal can be applied to each electromagnetic structure (13) by means of the driving circuit. Stress generated by a transfer carrier plate (20) according to the magnetic force of each electromagnetic structure (13) moves the transfer carrier plate (20). When the transfer carrier plate (20) is stress balanced in each direction parallel to the surface of the transfer carrier plate (20), the light-emitting diode chip (21) is precisely aligned to corresponding contact electrodes (12).