A chip structure, a packaging structure and a manufacturing method of the chip structure are provided. The chip structure includes a base and an electrically conductive interconnection layer. An upper surface of the base is provided with a plurality of bonding pads, and at least two of the bonding pads have same properties. The electrically conductive interconnection layer includes a plurality of electrically conductive interconnection structures. The electrically conductive interconnection structure electrically connects the bonding pads having same properties, and is configured to be electrically connected with a pin on a packaging substrate.

Embodiments of bonded 3D memory devices and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a plurality of first NAND memory strings and a plurality of first BLs. At least one of the first BLs may be conductively connected to a respective one of the first NAND memory strings. The first semiconductor structure also includes a plurality of first conductor layers, and a first bonding layer having a plurality of first bit line bonding contacts conductively connected to the plurality of first BLs and a plurality of first word line bonding contacts conductively connected to the first conductor layers. A second semiconductor structure includes a plurality of second NAND memory strings and a plurality of second BLs.

Semiconductor devices, such as memory devices, and associated systems and methods, are disclosed herein. A representative memory device includes a substrate including circuitry, back-end contacts electrically coupled to the circuitry, and front-end contacts. The front-end contacts are configured to receive electrical signals from an external device via a front-end interface. Individual ones of the front-end contacts are electrically coupled to and aligned along an axis with corresponding ones of the back-end contacts.

A radio frequency module includes a mounting substrate including a first main surface and a second main surface opposite to the first main surface. A first electronic component is disposed on the first main surface of the mounting substrate. A second electronic component is disposed on the second main surface of the mounting substrate. A plurality of connection terminals are disposed on the second main surface of the mounting substrate. A wiring layer faces the second main surface of the mounting substrate. The wiring layer includes a plurality of external connection electrodes, each connected to at least one of the second electronic component and the plurality of connection terminals. At least one of the plurality of external connection electrodes overlaps the second electronic component when viewed in plan in a thickness direction of the substrate.

A semiconductor structure includes a die, a molding surrounding the die, a first dielectric layer disposed over the die and the molding, and a second dielectric layer disposed between the first dielectric layer and the die, and between the first dielectric layer and the molding. A material content ratio in the first dielectric layer is substantially greater than that in the second dielectric layer. In some embodiments, the material content ratio substantially inversely affects a mechanical strength of the first dielectric layer and the second dielectric layer.

A semiconductor structure includes a die, a molding surrounding the die, a first dielectric layer disposed over the die and the molding, and a second dielectric layer disposed between the first dielectric layer and the die, and between the first dielectric layer and the molding. A material content ratio in the first dielectric layer is substantially greater than that in the second dielectric layer. In some embodiments, the material content ratio substantially inversely affects a mechanical strength of the first dielectric layer and the second dielectric layer.

A semiconductor package includes a redistribution layer and a semiconductor chip provided on the redistribution layer having a first surface and a second surface opposite to the first surface. The semiconductor chip includes a first chip pad and a second chip pad which are exposed at the first surface. The semiconductor package further includes a capacitor chip disposed between the first surface and the redistribution layer and including a capacitor chip pad connected to the first chip pad, an insulating layer covering the first surface and the capacitor chip, and a conductive post being in contact with the second chip pad and penetrating the insulating layer so as to be connected to the redistribution layer. The conductive post may be spaced apart from the capacitor chip.

A first semiconductor die and a second semiconductor die can be bonded in a manner that enhances alignment of bonding pads. Non-uniform deformation of a first wafer including first semiconductor dies can be compensated for by forming a patterned stress-generating film on a backside of the first wafer. Metallic bump portions can be formed on concave surfaces of metallic bonding pads by a selective metal deposition process to reduce gaps between pairs of bonded metallic bonding pads. Pad-to-pad pitch can be adjusted on a semiconductor die to match the pad-to-pad pitch of another semiconductor die employing a tilt-shift operation in a lithographic exposure tool. A chuck configured to provide non-uniform displacement across a wafer can be employed to hold a wafer in a contoured shape for bonding with another wafer in a matching contoured position. Independently height-controlled pins can be employed to hold a wafer in a non-planar configuration.

A semiconductor device includes a first substrate, a logical circuit, a first insulating film, a wiring, a plug, and a first layer containing a metal oxide or a metal nitride. The logical circuit is disposed on the first substrate. The first insulating film is disposed above the logical circuit. The wiring includes a first film disposed in the first insulating film, the first film extending in a first direction along an upper surface of the first substrate, and the first film containing a metal, and a first metal layer disposed in the first insulating film via the first film. The plug is disposed under the wiring, extends in a second direction that intersects the first direction, and is electrically connected to the wiring. The first layer is provided between an upper end of the plug and a bottom end of the wiring.

Embodiments of bonded 3D memory devices and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a plurality of first NAND memory strings and a plurality of first BLs. At least one of the first BLs may be conductively connected to a respective one of the first NAND memory strings. The first semiconductor structure also includes a plurality of first conductor layers, and a first bonding layer having a plurality of first bit line bonding contacts conductively connected to the plurality of first BLs and a plurality of first word line bonding contacts conductively connected to the first conductor layers. A second semiconductor structure includes a plurality of second NAND memory strings and a plurality of second BLs.