Integrated circuit (IC) device substrates and structures for mating and aligning with sockets. An IC device may include a frame on and around a substrate, which may include glass or silicon. The frame may include an alignment feature, such as a notch or hole, to mate with a complementary keying feature of a socket. A heat spreader may be coupled to an IC die and extend beyond the substrate or be coupled to the frame. The heat spreader may include a heat pipe. The IC device may be part of an IC system with the device substrate coupled to a system substrate by a socket configured to mate to the frame.

Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.

In one example, an electronic device includes a lower substrate comprising a lower substrate upper side and a lower substrate lower side, and an upper substrate comprising an upper substrate upper side and an upper substrate lower side. The electronic device also includes a first electronic component and a second electronic component coupled to the upper substrate upper side. A first device interconnect and a second device interconnect couple the lower substrate upper side to the upper substrate lower side. The electronic device also includes a connect die coupled to the lower substrate upper side that electrically couples the first electronic component to the second electronic component. Other examples and related methods are also disclosed herein.

A micro light emitting diode (LED) chip includes: a first semiconductor layer doped with an N-type dopant; a second semiconductor layer provided at a lower surface of the first semiconductor layer, and doped with a P-type dopant; an active layer provided between the first semiconductor layer and the second semiconductor layer, and configured to emit light; and an electrode pad provided at a lower surface of the second semiconductor layer, wherein the electrode pad may include a groove structure having a depth that increases from an edge of the electrode pad towards a center of the electrode pad.

Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.

In described examples, an integrated circuit includes a leadframe structure, which includes electrical conductors. A first coil structure is electrically connected to a first pair of the electrical conductors of the leadframe structure. The first coil structure is partially formed on a semiconductor die structure. A second coil structure is electrically connected to a second pair of the electrical conductors of the leadframe structure. The second coil structure is partially formed on the semiconductor die structure. A molded package structure encloses portions of the leadframe structure. The molded package structure exposes portions of the first and second pairs of the electrical conductors to allow external connection to the first and second coil structures. The molded package structure includes a cavity to magnetically couple portions of the first and second coil structures.

An integrated circuit includes a semiconductor die, a package substrate having opposite first and second surfaces, where the first surface includes a first metal pad, the second surface includes a second metal pad and a third metal pad. The semiconductor die is mounted on the second metal pad and the third metal pad by respective first and second metal interconnects. The package substrate includes a circuit with a single-ended terminal and a pair of differential terminals, where the single-ended terminal coupled to the first metal pad. The backage substrate also includes a metal layer including a first meandered conductor and a second meandered conductor. The first meandered conductor is coupled between a first terminal of the pair of differential terminals and the second metal pad. The second meandered conductor is coupled between a second terminal of the pair of differential terminals and the third metal pad.

A semiconductor package includes a substrate, a semiconductor die, a ring structure and a lid. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, where a first side of the semiconductor die is distant from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is distant from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is less than the second gap. The lid is disposed on the ring structure and has a recess formed therein, and the recess overlaps with the first gap in a stacking direction of the ring structure and the lid.

Disclosed examples include integrated circuits with a leadframe structure, a first circuit structure including a light source configured to generate a light signal along an optical path, a second circuit structure including a light sensor facing the optical path to receive the light signal, and a molded package structure enclosing portions of the leadframe structure, the molded package structure having a cavity defined by an interior surface of the molded package structure, the optical path extending in the cavity between the first and second circuit structures.

Semiconductor devices and methods are provided. In one example, a semiconductor device includes an active region comprising one or more active semiconductor cells. The semiconductor device includes a metallization structure on the active region. The metallization structure includes beryllium.