A first wafer includes a first semiconductor layer and first metal contacts on a side of a first surface of the first semiconductor layer. A second wafer includes a second semiconductor layer and second metal contacts on a side of a first surface of the second semiconductor layer. A handle is bonded onto a surface of the second wafer opposite to the second semiconductor layer. The second semiconductor layer is then removed to expose the second metal contacts. A bonding is then performed between the first and second wafers to electrically connect the first metal contacts to the second metal contacts.

A metal-dielectric bonding method includes providing a first semiconductor structure including a first semiconductor layer, a first dielectric layer on the first semiconductor layer, and a first metal layer on the first dielectric layer, where the first metal layer has a metal bonding surface facing away from the first semiconductor layer; planarizing the metal bonding surface; applying a plasma treatment on the metal bonding surface; providing a second semiconductor structure including a second semiconductor layer, and a second dielectric layer on the second semiconductor layer, where the second dielectric layer has a dielectric bonding surface facing away from the second semiconductor layer; planarizing the dielectric bonding surface; applying a plasma treatment on the dielectric bonding surface; and bonding the first semiconductor structure with the second semiconductor structure by bonding the metal bonding surface with the dielectric bonding surface.

A metal-dielectric bonding method includes providing a first semiconductor structure including a first semiconductor layer, a first dielectric layer on the first semiconductor layer, and a first metal layer on the first dielectric layer, where the first metal layer has a metal bonding surface facing away from the first semiconductor layer; planarizing the metal bonding surface; applying a plasma treatment on the metal bonding surface; providing a second semiconductor structure including a second semiconductor layer, and a second dielectric layer on the second semiconductor layer, where the second dielectric layer has a dielectric bonding surface facing away from the second semiconductor layer; planarizing the dielectric bonding surface; applying a plasma treatment on the dielectric bonding surface; and bonding the first semiconductor structure with the second semiconductor structure by bonding the metal bonding surface with the dielectric bonding surface.

A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.

A method for soldering a surface-mount component onto a circuit board. The melting of die-bonding solder material is prevented by using a mounting solder material when soldering a surface-mount component formed using the die-bonding solder material onto a printed circuit board. The surface-mount component, formed using (SnSb)-based solder material having high melting point, the (SnSb)-based solder material containing Cu but not more than a predetermined quantity of Cu constituent and a main ingredient thereof being Sn, is soldered on a board terminal portion of a circuit board using (SnAgCuBi)-based solder material or (SnAgCuBiIn)-based solder material as the mounting solder material and with the solder material being applied on the terminal portion. Since solidus temperature of the die-bonding solder material is 243 degrees C. and liquidus temperature of the mounting solder material is about 215 through 220 degrees C., the melting of die-bonding solder material is prevented even at the heating temperature (240 degrees C. or less) of a reflow furnace.

A method for making a semiconductor device includes providing a releasable carrier attached to a conductive layer, patterning a conductive circuit on a surface of the conductive layer, applying an insulative material at least partially covering the conductive circuit, releasing the releasable carrier from the conductive layer, and facilitating the releasing with an activating source. A method of fabricating a releasable carrier includes providing a supporting carrier, attaching a releasable tape to the supporting carrier, providing a first conductive layer and a second conductive layer attached to the first conductive layer, and attaching the first conductive layer to the releasable tape, where the releasable tape is configured to release the supporting carrier from the first conductive layer after being exposed to an activating source.

Disclosed herein is a releasable carrier that includes a supporting carrier, a carrier conductive layer, and a releasable tape located between the supporting carrier and the carrier conductive layer. The releasable tape attaches the supporting carrier to the carrier conductive layer. The releasable tape is configured to release the supporting carrier from the carrier conductive layer after being exposed to an activating source. The releasable carrier further includes a thin conductive layer attached to the carrier conductive layer, the thin conductive layer creating a surface configured to receive a conductive circuit. Further disclosed is a method for fabricating the releasable carrier and a method for making a semiconductor device using the releasable carrier.

A three-dimensional (3D) bonded semiconductor structure is provided in which a first bonding oxide layer of a first semiconductor structure is bonded to a second bonding oxide layer of a second semiconductor structure. Each of the first and second bonding oxide layers has a metallic bonding structure embedded therein, wherein each metallic bonding structure contains a columnar grain microstructure. Furthermore, at least one columnar grain extends across a bonding interface that is present between the metallic bonding structures. The presence of the columnar grain microstructure in the metallic bonding structures, together with at least one columnar grain microstructure extending across the bonding interface between the two bonded metallic bonding structures, can provide a 3D bonded structure having mechanical bonding strength and electrical performance enhancements.

The melting of die-bonding solder material is prevented even when soldering a surface-mount component formed using the die-bonding solder material on a printed circuit board using a mounting solder material. The surface-mount component formed using (SnSb)-based solder material having high melting point as the solder material for die pad, the (SnSb)-based solder material containing Cu not more than a predetermined quantity of Cu constituent and a main ingredient thereof being Sn, is soldered on a board terminal portion of a circuit board using (SnAgCuBi)-based solder material as the mounting solder material with the solder material being applied on the terminal portion. The melting of die-bonding solder material is prevented even at the heating temperature (240 degrees C. or less) of a reflow furnace.

A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.