A method for a through-silicon-via (TSV) connector includes: providing a semiconductor wafer with a silicon substrate, wherein the semiconductor wafer has a frontside and a backside opposite to the frontside thereof; forming multiple holes in the silicon substrate of the semiconductor wafer; forming a first insulating layer at a sidewall and bottom of each of the holes; forming a metal layer over the semiconductor wafer and in each of the holes; polishing the metal layer outside each of the holes to expose a frontside surface of the metal layer in each of the holes; forming multiple metal bumps or pads each on the frontside surface of the metal layer in at least one of the holes; grinding a backside of the silicon substrate of the semiconductor wafer to expose a backside surface of the metal layer in each of the holes, wherein the backside surface of the metal layer in each of the holes and a backside surface of the silicon substrate of the semiconductor wafer are coplanar; and cutting the semiconductor wafer to form multiple through-silicon-via (TSV) connectors.

A flip chip includes a substrate, an electrode pad layer stacked over the substrate, a passivation layer stacked at both ends of the electrode pad layer, an under bump metallurgy (UBM) layer stacked over the electrode pad layer and the passivation layer, and a bump formed over the UBM layer. The width of an opening on which the passivation layer is not formed over the electrode pad layer is greater than the width of the bump. The flip chip can prevent a crack from being generated in the pad upon ultrasonic bonding.

A semiconductor structure includes a first dielectric layer over a metal line and a redistribution layer (RDL) over the first dielectric layer. The RDL is electrically connected to the metal line. The RDL has a curved top surface and a footing feature, where the footing feature extends laterally from a side surface of the RDL. A second dielectric layer is disposed over the RDL, where the second dielectric layer also has a curved top surface.

A semiconductor package includes a leadframe forming a plurality of leads with a die attach site, a semiconductor die including a set of die contacts mounted to the die attach site in a flip chip configuration with each die contact of the set of die contacts electrically connected to leadframe via one of a set of solder joints, a set of solder joint capsules covering each of the set of solder joints against the leadframe, a clip mounted to the leadframe over the semiconductor die with a clip solder joint. The solder joint capsules restrict flow of the solder joints of the semiconductor die contacts in the flip chip configuration such that the solder remains in place if remelted during later clip solder reflow.

Semiconductor packages may include a first semiconductor chip including a first through-electrode and a first upper connection pad and on an upper surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip and including a second lower connection pad on a lower surface of the second semiconductor chip, a connection bump between the first and second semiconductor chips and connected to the first upper connection pad and the second lower connection pad, a first insulating layer between the first and second semiconductor chips and surrounding the first upper connection pad, the connection bump, and the second lower connection pad, and a second insulating layer between the first semiconductor chip and the first insulating layer and extending on the upper surface of the first semiconductor chip, a side surface of the first upper connection pad, and a portion of a side surface of the connection bump.

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a bump and a first dummy bump between the chip and the substrate. The bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, and the first dummy bump is wider than the bump. The chip package structure includes a first dummy solder layer under the first dummy bump and having a curved bottom surface facing and spaced apart from the substrate.

An integrated circuit device includes a semiconductor substrate; and a pad region over the semiconductor substrate. The integrated circuit device further includes an under-bump-metallurgy (UBM) layer over the pad region. The integrated circuit device further includes a conductive pillar on the UBM layer, wherein the conductive pillar has a sidewall surface and a top surface. The integrated circuit device further includes a protection structure over the sidewall surface of the conductive pillar, wherein sidewalls of the UBM layer are substantially free of the protection structure, and the protection structure is a non-metal material.

A positive-type photosensitive resin composition includes (A) a phenol resin modified by a compound having an unsaturated hydrocarbon group having 4 to 100 carbon atoms; (B) a compound that produces an acid by light; (C) a thermal crosslinking agent; and (D) a solvent. The positive-type photosensitive resin composition according to the present invention can be developed by an alkaline aqueous solution, and an effect thereof is that a resist pattern having sufficiently high sensitivity and resolution, excellent adhesion, and good thermal shock resistance can be formed.

A method of hybridizing an FPA having an IR component and a ROIC component and interconnects between the two components, includes the steps of: providing an IR detector array and a Si ROIC; depositing a dielectric layer on both the IR detector array and on the Si ROIC; patterning the dielectric on both components to create openings to expose contact areas on each of the IR detector array and the Si ROIC; depositing indium to fill the openings on both the IR detector array and the Si ROIC to create indium bumps, the indium bumps electrically connected to the contact areas of the IR detector array and the Si ROIC respectively, exposed on a top surface of the IR detector array and the Si ROIC; activating exposed dielectric layers on the IR detector array and the Si ROIC in a plasma; and closely contacting the indium bumps of the IR detector array and the Si ROIC by bonding together the exposed dielectric surfaces of the IR detector array and the Si ROIC. Another exemplary method provides a pillar support of the indium bumps on the IR detector array rather than a full dielectric layer support. Another exemplary method includes a surrounding dielectric edge support between the IR detector array and the Si ROIC with the pillar supports.

A device package includes a die and a molding compound around the die. The molding compound has a non-planar surface recessed from a top surface of the die. The device package also includes an interconnect structure over the die. The interconnect structure includes a redistribution layer extending onto the molding compound and conformal to the non-planar surface of the molding compound. The device package further includes a first connector disposed over the die and bonded to the interconnect structure.