Semiconductor devices having an array of flexible connectors configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor assembly includes a substrate coupled to an array of flexible connectors. Each flexible connector can be transformed between a resting configuration and a loaded configuration. Each flexible connector can include a conductive wire electrically coupled to the substrate and a support material at least partially surrounding the conductive wire. The conductive wire can have a first shape when the flexible connector is in the resting configuration and a second, different shape when the flexible connector is in the loaded configuration.

A microelectronic device has bump bonds and an inductor on a die. The microelectronic device includes first lateral conductors extending along a terminal surface of the die, wherein at least some of the first lateral conductors contact at least some of terminals of the die. The microelectronic device also includes conductive columns on the first lateral conductors, extending perpendicularly from the terminal surface, and second lateral conductors on the conductive columns, opposite from the first lateral conductors, extending laterally in a plane parallel to the terminal surface. A first set of the first lateral conductors, the conductive columns, and the second lateral conductors provide the bump bonds of the microelectronic device. A second set of the first lateral conductors, the conductive columns, and the second lateral conductors are electrically coupled in series to form the inductor. Methods of forming the microelectronic device are also disclosed.

A semiconductor device assembly includes a package substrate having a top side including a plurality of bondable features, at least one integrated circuit (IC) die including a substrate having at least a semiconductor surface including circuitry configured for realizing at least one function including nodes coupled to bond pads with metal posts on the bond pads. The metal posts are attached by a solder joint to the bondable features. The solder joint has a void density of less than or equal to (≥) 5% of a cross-sectional area of the solder joint.

A semiconductor device assembly includes a package substrate having a top side including a plurality of bondable features, at least one integrated circuit (IC) die including a substrate having at least a semiconductor surface including circuitry configured for realizing at least one function including nodes coupled to bond pads with metal posts on the bond pads. The metal posts are attached by a solder joint to the bondable features. The solder joint has a void density of less than or equal to (≥) 5% of a cross-sectional area of the solder joint.

A semiconductor device of an embodiment includes: a first semiconductor element; a first insulating resin that seals the first semiconductor element; a wiring substrate having a pad; a first wiring that extends from the first semiconductor element toward the wiring substrate, and has a first head portion and a first column portion, the first column portion connected to the first semiconductor element and the first head portion exposed on a surface of the first insulating resin; and a first conductive bonding agent that electrically connects the first head portion of the first wiring and the pad. When a surface of the first head portion facing a side of the first insulating resin is defined as a first surface. A surface of the first insulating resin on a side of the wiring substrate is defined as a second surface. A distance from a surface of the wiring substrate on a side of the first insulating resin to the first surface is defined as a first distance, and a distance from a surface of the wiring substrate on the side of the first insulating resin to the second surface is defined as a second distance. The first distance is shorter than the second distance.

Provided is a method of manufacturing a semiconductor package, the method including a first step for forming a primary solder ball on an under bump metallurgy (UBM) structure, and a second step for forming a secondary solder ball on an upper surface of the UBM structure by performing a reflow process on the primary solder ball while a side wall of the UBM structure is exposed.

The connection method between at least two elements (E1, E2) corresponding to a printed circuit (4) and to an electronic component (5), comprises a step of forming a plurality of pad-type stacks (2) of bosses (3), the stacks (2) of bosses (3) being formed on a face (10) of a first (E1) of the elements (E1, E2), the stacks (2) of bosses (3) each comprising the same given number of bosses (3), said method also comprising a step of depositing a brazing product (7) on this first element (E1) provided with stacks (2) of bosses (3), a step of arranging the second (E2) of the elements (E1, E2) on the first element (E1), and a step of remelting the assembly thus formed, in order to obtain an electronic device (1). This method makes it possible to produce a precise and flexible raising of surface mounted electronic components.

A method for fabricating a resist structure is presented. The method includes preparing a substrate on which plural conductive pads are formed; and patterning a lower resist to form plural lower cavities. The lower resist is deposited above the substrate. Each of the plural lower cavities are located above a corresponding one of the plural conductive pads. Additionally, the method includes patterning an upper resist to form plural upper cavities. The upper resist is deposited on the lower resist. Each of the plural upper cavities are located on a corresponding one of the plural lower cavities and have a diameter larger than a diameter of the corresponding one of the plural lower cavities.

A microelectronic device includes a die with input/output (I/O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically conductive pillars which are electrically coupled to the I/O terminals, and extend through the dielectric layer to an exterior of the microelectronic device. Each pillar includes a column electrically coupled to one of the I/O terminals, and a head contacting the column at an opposite end of the column from the I/O terminal. The head extends laterally past the column in at least one lateral direction. Methods of forming the pillars and the dielectric layer are disclosed.

Devices and methods that can facilitate hybrid under-bump metallization components are provided. According to an embodiment, a device can comprise an under-bump metallization component that can comprise a superconducting interconnect component and a solder wetting component. The device can further comprise a solder bump that can be coupled to the superconducting interconnect component and the solder wetting component. In some embodiments, the superconducting interconnect component can comprise a hermetically sealed superconducting interconnect component.