A method for manufacturing a semiconductor device includes forming a thermosetting resin film on a first metal layer, forming an opening in the resin film, forming a second metal layer that covers a region from an upper surface of the first metal layer exposed from the opening of the resin film to an upper surface of the resin film, performing heat treatment at a temperature equal to or higher than a temperature at which the resin film is cured after forming the second metal layer, forming a cover film that covers the upper surface of the resin film and a side surface of the second metal layer after performing the heat treatment, and forming a solder on an upper surface of the second metal layer exposed from an opening of the cover film after forming the cover film.

Methods for die attachment of multichip and single components including flip chips may involve printing a sintering paste on a substrate or on the back side of a die. Printing may involve stencil printing, screen printing, or a dispensing process. Paste may be printed on the back side of an entire wafer prior to dicing, or on the back side of an individual die. Sintering films may also be fabricated and transferred to a wafer, die or substrate. A post-sintering step may increase throughput.

A method for printing solder onto a wafer (101) including the steps of depositing solder paste (102) onto a wafer (101), applying an inline reflow process to the deposited solder paste (102) to form solder bumps (103) on the wafer (101), and cleaning the reflowed solder bumps (103). The method for printing solder onto the wafer (101) is based on a system thereof that includes a wafer solder printer (1), an inline reflow means (2) and a de-fluxing means (3), wherein each step has its parameters optimized by means of a staging process control.

A solder member mounting method includes providing a substrate having bonding pads formed thereon, detecting a pattern interval of the bonding pads, selecting one of solder member attachers having different pattern intervals from each other, such that the one selected solder member attacher of the solder member attachers has a pattern interval corresponding to the detected pattern interval of the bonding pads, and attaching solder members on the bonding pads of the substrate, respectively, using the one selected solder member attacher.

A solder member mounting method includes providing a substrate having bonding pads formed thereon, detecting a pattern interval of the bonding pads, selecting one of solder member attachers having different pattern intervals from each other, such that the one selected solder member attacher of the solder member attachers has a pattern interval corresponding to the detected pattern interval of the bonding pads, and attaching solder members on the bonding pads of the substrate, respectively, using the one selected solder member attacher.

An electronic device includes a substrate having top side contact pads including metal pillars thereon or a laminate substrate having land pads with the pillars thereon. A solder including layer stack is on the pillars, the solder including layer stack having a bottom solder material layer including in physical contact with a top surface of the pillars, a metal material layer, and a capping solder material layer on the metal material layer. The metal material layer is primarily a copper layer or an intermetallic compound (IMC) layer including copper.

An electronic device includes a substrate having top side contact pads including metal pillars thereon or a laminate substrate having land pads with the pillars thereon. A solder including layer stack is on the pillars, the solder including layer stack having a bottom solder material layer including in physical contact with a top surface of the pillars, a metal material layer, and a capping solder material layer on the metal material layer. The metal material layer is primarily a copper layer or an intermetallic compound (IMC) layer including copper.

Methods of reflowing electrically conductive elements on a wafer may involve directing a laser beam toward a region of a surface of a wafer supported on a film of a film frame to reflow at least one electrically conductive element on the surface of the wafer. In some embodiments, the wafer may be detached from a carrier substrate and be secured to the film frame before laser reflow. Apparatus for performing the methods, and methods of repairing previously reflowed conductive elements on a wafer are also disclosed.

A package structure including a semiconductor die, an insulating encapsulant, and a redistribution layer is provided. The semiconductor die includes a semiconductor substrate, a plurality of metallization layers disposed on the semiconductor substrate, and a passivation layer disposed on the plurality of metallization layers. The passivation layer has a first opening that partially expose a topmost layer of the plurality of metallization layers. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer includes at least a first dielectric layer and a first conductive layer stacked on the first dielectric layer. The first dielectric layer has a second opening that overlaps with the first opening, and a width ratio of the second opening to the first opening is in a range of 2.3:1 to 12:1. The first conductive layer is electrically connected to the topmost layer of the plurality of metallization layers through the first and second openings.

A package structure including a semiconductor die, an insulating encapsulant, and a redistribution layer is provided. The semiconductor die includes a semiconductor substrate, a plurality of metallization layers disposed on the semiconductor substrate, and a passivation layer disposed on the plurality of metallization layers. The passivation layer has a first opening that partially expose a topmost layer of the plurality of metallization layers. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer includes at least a first dielectric layer and a first conductive layer stacked on the first dielectric layer. The first dielectric layer has a second opening that overlaps with the first opening, and a width ratio of the second opening to the first opening is in a range of 2.3:1 to 12:1. The first conductive layer is electrically connected to the topmost layer of the plurality of metallization layers through the first and second openings.