A semiconductor package includes a first die, a second die, a molding compound and a redistribution structure. The first die has a first conductive pillar and a first complex compound sheath surrounding and covering a sidewall of the first conductive pillar. The second die has a second conductive pillar and a protection layer laterally surrounding the second conductive pillar. The molding compound laterally surrounds and wraps around the first and second dies, and is in contact with the first complex compound sheath of the first die. The redistribution structure is disposed on the first and second dies and the molding compound.

A semiconductor package structure includes a semiconductor die surface having a narrower pitch region and a wider pitch region adjacent to the narrower pitch region, a plurality of first type conductive pillars in the narrower pith region, each of the first type conductive pillars having a copper-copper interface, and a plurality of second type conductive pillars in the wider pitch region, each of the second type conductive pillars having a copper-solder interface. A method for manufacturing the semiconductor package structure described herein is also disclosed.

An electronic device is disclosed. In an embodiment an electronic device includes a carrier board having an upper surface and an electronic chip mounted on the upper surface of the carrier board, the electronic chip having a mounting side facing the upper surface of the carrier board, a top side facing away from the upper surface of the carrier board, and sidewalls connecting the mounting side to the top side, wherein the electronic chip has equal to or less than 5 stud bumps per square millimeter of a base area of the mounting side, and wherein a laminated polymer hood at least partly covers the top side of the electronic chip and extends onto the upper surface of the carrier board.

Embodiments for a packaged semiconductor device and methods of making are provided herein, which includes a packaged semiconductor device including: a semiconductor die; a carrier; a plurality of electrical connections formed between the semiconductor die and the carrier; an electrical isolation layer that covers an outer surface of each of the plurality of electrical connections; and a conductive underfill structure between the semiconductor die and the carrier, and surrounding each of the plurality of electrical connections, wherein the electrical isolation layer electrically isolates each electrical connection from the conductive underfill structure.

An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.

An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.

A method for electrically coupling a pad and a front face of a pillar, including shaping the front face pillar, the front face having at least partially a convex surface, applying a suspension to the front face or to the pad, wherein the suspension includes a carrier fluid, electrically conducting microparticles and electrically conducting nanoparticles, arranging the front face of the pillar opposite to the pad at a distance such that the carrier fluid bridges at least partially a gap between the front face of the pillar and the pad, evaporating the carrier fluid thereby confining the microparticles and the nanoparticles, and thereby arranging the nanoparticles and the microparticles as percolation paths between the front face of the pillar and the pad, and sintering the arranged nanoparticles for forming metallic bonds at least between the nanoparticles and/or between the nanoparticles and the front face of the pillar or the pad.

A semiconductor package includes a first die, a second die, a molding compound and a redistribution structure. The first die has a first conductive pillar and a first complex compound sheath surrounding and covering a sidewall of the first conductive pillar. The second die has a second conductive pillar and a protection layer laterally surrounding the second conductive pillar. The molding compound laterally surrounds and wraps around the first and second dies, and is in contact with the first complex compound sheath of the first die. The redistribution structure is disposed on the first and second dies and the molding compound. The redistribution structure has a first via portion embedded in the first polymer dielectric layer and a second via portion embedded in the second polymer dielectric layer. A base angle of the first via portion is greater than a base angle of the second via portion.

The present invention is directed to a method for interconnecting two components. The first component includes a first substrate and a set of structured metal pads arranged on a main surface. Each of the pads includes one or more channels, extending in-plane with an average plane of the pad, so as to form at least two raised structures. The second interconnect component includes a second substrate and a set of metal pillars arranged on a main surface. The structured metal pads are bonded to a respective, opposite one of the metal pillars, using metal paste. The paste is sintered to form porous metal joints at the level of the channels. Metal interconnects are obtained between the substrates. During the bonding, the metal paste is sintered by exposing the structured metal pads and metal pillars to a reducing agent. The channels and raised structures improve the penetration of the reducing agent.

The present invention is directed to a method for interconnecting two components. The first component includes a first substrate and a set of structured metal pads arranged on a main surface. Each of the pads includes one or more channels, extending in-plane with an average plane of the pad, so as to form at least two raised structures. The second interconnect component includes a second substrate and a set of metal pillars arranged on a main surface. The structured metal pads are bonded to a respective, opposite one of the metal pillars, using metal paste. The paste is sintered to form porous metal joints at the level of the channels. Metal interconnects are obtained between the substrates. During the bonding, the metal paste is sintered by exposing the structured metal pads and metal pillars to a reducing agent. The channels and raised structures improve the penetration of the reducing agent.