A semiconductor device according to the embodiment may include a light emitting structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer; a first bonding pad disposed on the light emitting structure and electrically connected to the first conductivity type semiconductor layer; a second bonding pad disposed on the light emitting structure and spaced apart from the first bonding pad, and electrically connected to the second conductivity type semiconductor layer; and a reflective layer disposed on the light emitting structure and disposed between the first bonding pad and the second bonding pad. According to the semiconductor device of the embodiment, each of the first bonding pad and the second bonding pad includes a porous metal layer having a plurality of pores and a bonding alloy layer disposed on the porous metal layer.

A semiconductor device according to the embodiment may include a light emitting structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer; a first bonding pad disposed on the light emitting structure and electrically connected to the first conductivity type semiconductor layer; a second bonding pad disposed on the light emitting structure and spaced apart from the first bonding pad, and electrically connected to the second conductivity type semiconductor layer; and a reflective layer disposed on the light emitting structure and disposed between the first bonding pad and the second bonding pad. According to the semiconductor device of the embodiment, each of the first bonding pad and the second bonding pad includes a porous metal layer having a plurality of pores and a bonding alloy layer disposed on the porous metal layer.

A semiconductor device includes a substrate having a plurality of pads on a surface of the substrate, a semiconductor chip that includes a plurality of metal bumps connected to corresponding pads on the substrate, a first resin layer between the surface of the substrate and the semiconductor chip, a second resin layer between the substrate and the semiconductor chip and between the first resin layer and at least one of the metal bumps, and a third resin layer on the substrate and above the semiconductor chip.

A copper pillar bump for an electrode pad of a semiconductor chip includes a first copper layer, a first metal layer formed directly on the first copper layer, a second copper layer formed directly on the first metal layer, and a second metal layer formed directly on the second copper layer, wherein the first metal layer and the second metal layer are made of a metal having a different etching rate than copper, wherein an outer perimeter ring of the first metal layer protrudes beyond a lateral surface of the first copper layer, and wherein an outer perimeter ring of the second metal layer protrudes beyond a lateral surface of the second copper layer.

A copper pillar bump for an electrode pad of a semiconductor chip includes a first copper layer, a first metal layer formed directly on the first copper layer, a second copper layer formed directly on the first metal layer, and a second metal layer formed directly on the second copper layer, wherein the first metal layer and the second metal layer are made of a metal having a different etching rate than copper, wherein an outer perimeter ring of the first metal layer protrudes beyond a lateral surface of the first copper layer, and wherein an outer perimeter ring of the second metal layer protrudes beyond a lateral surface of the second copper layer.

Embodiments relate to the design of a device capable of maintaining the alignment an interconnect by resisting lateral forces acting on surfaces of the interconnect. The device comprises a first body comprising a first surface with a nanoporous metal structure protruding from the first surface. The device further comprises a second body comprising a second surface with a locking structure to resist a lateral force between the first body and the second body during or after assembly of the first body and the second body.

A semiconductor package includes a plurality of metal leads and a semiconductor die attached to the plurality of metal leads by an interconnect. A surface of the plurality of metal leads, a metallized surface of the semiconductor die, and/or a surface of the interconnect comprises Cu and has a thermal conductivity in a range of 340 to 400 W/mK and an electrical conductivity in a range of 80 to 110% IACS. One or more of the surfaces which comprise Cu and have a thermal conductivity in the range of 340 to 400 W/mK and an electrical conductivity in the range of 80 to 110% IACS also includes micropores having a diameter in a range of 1 m to 10 m. A method of manufacturing a metal surface with such micropores also is described.

A method for forming a package structure includes forming an under bump metallization (UBM) layer over a metal pad and forming a photoresist layer over the UBM layer. The method further includes patterning the photoresist layer to form an opening in the photoresist layer. The method also includes forming a first bump structure over the first portion of the UBM layer. The first bump structure includes a first barrier layer over a first pillar layer. The method includes placing a second bump structure over the first bump structure. The second bump structure includes a second barrier layer over a second pillar layer. The method further includes reflowing the first bump structure and the second bump structure to form a solder joint between a first inter intermetallic compound (IMC) and a second IMC.

A semiconductor package includes an electrical connection structure. The electrical connection structure includes: a first conductive layer; a second conductive layer on the first conductive layer; and a conductive cap between the first conductive layer and the second conductive layer, the conductive cap having a hardness greater than a hardness of the first conductive layer.

A semiconductor package includes an electrical connection structure. The electrical connection structure includes: a first conductive layer; a second conductive layer on the first conductive layer; and a conductive cap between the first conductive layer and the second conductive layer, the conductive cap having a hardness greater than a hardness of the first conductive layer.