A package structure is provided. The package structure includes a first bump structure formed over a substrate, a solder joint formed over the first bump structure and a second bump structure formed over the solder joint. The first bump structure includes a first pillar layer formed over the substrate and a first barrier layer formed over the first pillar layer. The first barrier layer has a first protruding portion which extends away from a sidewall surface of the first pillar layer, and a distance between the sidewall surface of the first pillar layer and a sidewall surface of the first barrier layer is in a range from about 0.5 m to about 3 m. The second bump structure includes a second barrier layer formed over the solder joint and a second pillar layer formed over the second barrier layer, wherein the second barrier layer has a second protruding portion which extends away from a sidewall surface of the second pillar layer.

A wiring board includes a semiconductor chip mounting surface, an external connection surface provided on an opposite side from the semiconductor chip mounting surface, and pads provided on the semiconductor chip mounting surface. Each pad includes a columnar section, and a tapered section, continuously formed on a first end of the columnar section, and having a cross sectional area that decreases toward a direction away from the columnar section. The tapered section of each pad projects from the semiconductor chip mounting surface.

A semiconductor package includes a plurality of metal leads and a semiconductor die attached to the plurality of metal leads by an interconnect. A surface of the plurality of metal leads, a metallized surface of the semiconductor die, and/or a surface of the interconnect comprises Cu and has a thermal conductivity in a range of 340 to 400 W/mK and an electrical conductivity in a range of 80 to 110% IACS. One or more of the surfaces which comprise Cu and have a thermal conductivity in the range of 340 to 400 W/mK and an electrical conductivity in the range of 80 to 110% IACS also includes micropores having a diameter in a range of 1 m to 10 m. A method of manufacturing a metal surface with such micropores also is described.

In a described example, a method is described including: depositing a zinc seed layer on a substrate; forming a photoresist pattern on the zinc seed layer, with openings in the photoresist pattern exposing portions of the zinc seed layer; electroplating a copper structure onto the exposed portions of the zinc seed layer; stripping the photoresist; annealing the substrate to form copper/zinc alloy between the copper structure and the substrate; and etching away the unreacted portions of the zinc seed layer.

The present disclosure describes a coaxial-interconnect structure that is integrated into a semiconductor component and methods of forming the coaxial-interconnect structure. The coaxial interconnect-structure, which electrically couples circuitry of an integrated-circuit (IC) die to traces of a packaging substrate, comprises a signal core elongated about an axis, a ground shield elongated about the axis, and an insulator disposed between the signal core and the ground shield.

The present disclosure describes a coaxial-interconnect structure that is integrated into a semiconductor component and methods of forming the coaxial-interconnect structure. The coaxial interconnect-structure, which electrically couples circuitry of an integrated-circuit (IC) die to traces of a packaging substrate, comprises a signal core elongated about an axis, a ground shield elongated about the axis, and an insulator disposed between the signal core and the ground shield.

There are provided a semiconductor memory device and a method for manufacturing the same. The semiconductor memory device includes: a first substrate including a peripheral circuit, first conductive contact patterns connected to the peripheral circuit, and a first upper insulating layer having grooves exposing the first conductive contact patterns; a second substrate including a memory cell array, a second upper insulating layer disposed on the memory cell array, the second upper insulating layer formed between the memory cell array and the first upper insulating layer, a second conductive contact patterns protruding through the second upper insulating layer into an opening of the grooves; and conductive adhesive patterns filling the grooves to connect the second conductive contact patterns to the first conductive contact patterns.

The present invention relates to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.

Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

Methods, apparatuses, and systems related to embedded metal pads are described. An example semiconductor device includes a dielectric material, a metal pad having side surface, where a lower portion of the side surface is embedded in the dielectric material, a mask material on a portion of a surface of the dielectric material, an upper portion of the side surface of the metal pad, and a portion of a top surface of the metal pad and a contact pillar on a second portion of the top surface of metal pad, the contact pillar comprising a metal pillar and a pillar bump.