A semiconductor package includes a first semiconductor chip having a through-electrode and an upper connection pad on an upper surface of the first semiconductor chip that is connected to the through-electrode; a second semiconductor chip stacked on the first semiconductor chip, and having a lower connection pad on a lower surface of the second semiconductor chip; a non- conductive film between the first semiconductor chip and the second semiconductor chip, with the non-conductive film including voids having an average diameter of 1μm to 100 um, the voids having a volume fraction of 0.1 to 5 vol %; and a connection conductor that penetrates the non- conductive film and connects the upper connection pad and the lower connection pad.

A semiconductor package includes a first semiconductor chip having a through-electrode and an upper connection pad on an upper surface of the first semiconductor chip that is connected to the through-electrode; a second semiconductor chip stacked on the first semiconductor chip, and having a lower connection pad on a lower surface of the second semiconductor chip; a non-conductive film between the first semiconductor chip and the second semiconductor chip, with the non-conductive film including voids having an average diameter of 1 μm to 100 μm, the voids having a volume fraction of 0.1 to 5 vol %; and a connection conductor that penetrates the non-conductive film and connects the upper connection pad and the lower connection pad.

A semiconductor package includes a first semiconductor chip having a through-electrode and an upper connection pad on an upper surface of the first semiconductor chip that is connected to the through-electrode; a second semiconductor chip stacked on the first semiconductor chip, and having a lower connection pad on a lower surface of the second semiconductor chip; a non-conductive film between the first semiconductor chip and the second semiconductor chip, with the non-conductive film including voids having an average diameter of 1 m to 100 m, the voids having a volume fraction of 0.1 to 5 vol %; and a connection conductor that penetrates the non-conductive film and connects the upper connection pad and the lower connection pad.

The present application provides a semiconductor structure having a copper pillar within a solder bump, and a manufacturing method of the semiconductor structure. The semiconductor structure includes a substrate having a pad disposed thereon and a passivation at least partially surrounding the pad; and a conductive bump structure disposed over the passivation and the pad, wherein the conductive bump structure includes a first bump portion disposed over the passivation and the pad, a conductive pillar disposed over the first bump portion, and a second bump portion disposed over and surrounding the conductive pillar.

A semiconductor package includes an electrical connection structure. The electrical connection structure includes: a first conductive layer; a second conductive layer on the first conductive layer; and a conductive cap between the first conductive layer and the second conductive layer, the conductive cap having a hardness greater than a hardness of the first conductive layer.

A semiconductor package includes an electrical connection structure. The electrical connection structure includes: a first conductive layer; a second conductive layer on the first conductive layer; and a conductive cap between the first conductive layer and the second conductive layer, the conductive cap having a hardness greater than a hardness of the first conductive layer.

Implementations of a semiconductor package may include a die; a first pad and a second pad, the first pad and the second pad each including a first layer and a second layer where the second layer may be thicker than the first layer. At least a first conductor may be directly coupled to the second layer of the first pad; at least a second conductor may be directly coupled to the second layer of the second pad; and an organic material may cover at least the first side of the die. The at least first conductor and the at least second conductor extend through openings in the organic material where a spacing between the at least first conductor and the at least second conductor may be wider than a spacing between the second layer of the first pad and the second layer of the second pad.

Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, an interconnect structure includes a first conductive element, a second conductive element, and an intermetallic palladium joint. The intermetallic palladium joint includes an intermetallic crystallite spanning between the first and second conductive elements. The intermetallic crystallite includes a first end portion and a second end portion. The first end portion directly contacts the first conductive element. The second end portion directly contacts the second conductive element.

A copper pillar bump (CPB) structure is provided in the present invention, including a substrate, a pad on the substrate, a passivation layer covering the substrate and exposing the pad, and a copper pillar on the passivation layer and the pad and connecting directly with the pad. The copper pillar is provided with an upper part and a lower part, and a top surface of the lower part includes a first top surface and a second top surface. The second top surface is on one side of the first top surface, and the upper part of the copper pillar is on the first top surface of the lower part. A metal bump is on the copper pillar, wherein parts of the metal bump directly contact the second top surface of the lower part.

The present disclosure describes a coaxial-interconnect structure that is integrated into a semiconductor component and methods of forming the coaxial-interconnect structure. The coaxial interconnect-structure, which electrically couples circuitry of an integrated-circuit (IC) die to traces of a packaging substrate, comprises a signal core elongated about an axis, a ground shield elongated about the axis, and an insulator disposed between the signal core and the ground shield.