Patent classifications
H01L2224/1403
Localized high density substrate routing
Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.
Dummy die placement without backside chipping
A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.
Light-emitting device, manufacturing method thereof and display module using the same
The application discloses a light-emitting device including a carrier which includes an insulating layer, an upper conductive layer formed on the insulating layer, a plurality of conducting vias passing through the insulating layer, and a lower conductive layer formed under the insulating layer; four light-emitting elements arranged in rows and columns flipped on the carrier; and a light-passing unit formed on the carrier and covering the four light-emitting elements; wherein each of the light-emitting elements including a first light-emitting bare die emitting a first dominant wavelength, a second light-emitting bare die emitting a second dominant wavelength, and a third light-emitting bare die emitting a third dominant wavelength; and wherein two adjacent first light-emitting bare die in a row has a first distance W1, two adjacent first light-emitting bare die in a column has a second distance W2, and W1 is the same as W2.
Semiconductor device
A semiconductor device includes a first electronic component, a second electronic component, a third electronic component, a plurality of first interconnection structures, and a plurality of second interconnection structures. The second electronic component is between the first electronic component and the third electronic component. The first interconnection structures are between and electrically connected to the first electronic component and the second electronic component. Each of the first interconnection structures has a length along a first direction substantially parallel to a surface of the first electronic component and a width along a second direction substantially parallel to the surface and substantially perpendicular to the first direction. The length is larger than the width. The second interconnection structures are between and electrically connected to the second electronic component and the third electronic component.
Substrate thermal layer for heat spreader connection
A semiconductor device package structure is provided. The semiconductor device package structure includes a substrate having a first layer over a second layer. The first layer may have greater thermal conductivity than the second layer. The semiconductor device package structure further includes one or more dies coupled to the substrate. A heat spreader may have a first section coupled to a first surface of a first die of the one or more dies, and a second section coupled to the first layer.
Multi-die interconnect
Disclosed is an apparatus including a molded multi-die high density interconnect including: a bridge die having a first plurality of interconnects and second plurality of interconnects. The apparatus also includes a first die having a first plurality of contacts and a second plurality of contacts, where the second plurality of contacts is coupled to the first plurality of interconnects of the bridge die. The apparatus also includes a second die having a first plurality of contacts and a second plurality of contacts, where the second plurality of contacts is coupled to the second plurality of interconnects of the bridge die. The coupled second plurality of contacts and interconnects have a smaller height than the first plurality of contacts of the first die and second die.
DISPLAY DEVICE USING MICRO LED, AND MANUFACTURING METHOD THEREFOR
Disclosed in the present specification is a micro LED display device, and a manufacturing method therefor, the method forming, in advance, an anisotropic conductive adhesive paste layer only on a conductive electrode part of a semiconductor light emitting element and on a peripheral part thereof, and then transferring the anisotropic conductive adhesive paste layer to a wiring substrate, thereby simultaneously performing a transfer step and a stable wiring step.
SEMICONDUCTOR DEVICES AND PREPARATION METHODS THEREOF
The present disclosure provides a semiconductor device and a preparation method thereof. The semiconductor device comprises: a semiconductor substrate; a passivation layer, arranged on an upper surface of the semiconductor substrate; a protective layer, arranged on an upper surface of the passivation layer, a dummy opening being formed on the protective layer; and, a dummy bump, partially located in the dummy opening and closely attached to the protective layer.
SEMICONDUCTOR DEVICE INCLUDING RE-DISTRIBUTION PADS DISPOSED AT DIFFERENT LEVELS AND A METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a chip body; a passivation layer on the chip body; a lower dielectric layer on the passivation layer; a first re-distribution pad on the lower dielectric layer; an upper dielectric layer on the lower dielectric layer, the upper dielectric layer having a groove that exposes an upper surface of the first re-distribution pad; and a second re-distribution pad on the upper dielectric layer. An upper surface of the second re-distribution pad is positioned at a higher level than the upper surface of the first re-distribution pad.
Power amplifier module
A power amplifier module includes a substrate including, in an upper surface of the substrate, an active region and an element isolation region. The power amplifier module further includes a collector layer, a base layer, and an emitter layer that are stacked on the active region; an interlayer insulating film that covers the collector layer, the base layer, and the emitter layer; a pad that is thermally coupled to the element isolation region; and an emitter bump that is disposed on the interlayer insulating film, electrically connected to the emitter layer through a via hole provided in the interlayer insulating film, and electrically connected to the pad. In plan view, the emitter bump partially overlaps an emitter region which is a region of the emitter layer and through which an emitter current flows.