A multi-chip package structure includes a chip interconnect bridge, a fan-out redistribution layer structure, a first integrated circuit chip, and a second integrated circuit chip. The chip interconnect bridge includes contact pads disposed on a top side of the chip interconnect bridge. The fan-out redistribution layer structure is disposed around sidewalls of the chip interconnect bridge and over the top side of the chip interconnect bridge. The first and second integrated circuit chips are direct chip attached to an upper surface of the fan-out redistribution layer structure, wherein the fan-out redistribution layer structure includes input/output connections between the contact pads on the top side of the chip interconnect bridge and the first and second integrated circuit chips.

In one example, a semiconductor device comprises a first base substrate comprising a first base conductive structure, a first encapsulant contacting a lateral side of the first base substrate, a redistribution structure (RDS) substrate over the base substrate and comprising an RDS conductive structure coupled with the first base conductive structure, a first electronic component over the RDS substrate and over a first component terminal coupled with the RDS conductive structure, and a second encapsulant over the RDS substrate and contacting a lateral side of the first electronic component. Other examples and related methods are also disclosed herein.

Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes bumps to electrically couple the die to the substrate. Ones of the bumps have corresponding bases. The bases have a shape that is non-circular.

An electronic component includes a device die and a substrate. The device die includes conductive contacts with conductive pillars conductively affixed to conductive contact. The conductive pillars include a cavity formed in an end of the conductive pillar opposite the conductive contact. The substrate includes of conductive pads that are each associated with one of the conductive contacts. The conductive pads include a conductive pad conductively affixed to the substrate, and a conductive ring situated within a cavity in the end conductive rings have a capillary formed along an axis of the conductive ring. A solder material fills the capillary of each of the conductive rings and the cavity formed in the end of the associated conductive pillars to form a conductive joint between the pillars and the conductive pads.

Disclosed is a micro light-emitting component, a micro light-emitting diode, and a transfer layer. The transfer layer has a recess for receiving the micro light-emitting diode to permit the micro light-emitting diode to be retained by the transfer layer, and is transformable from a first state, in which the transfer layer is deformed by the micro light-emitting diode to form the recess, to a second state, in which the micro light-emitting diode received in the recess is retained by the transfer layer. Also disclosed are micro light-emitting component matrix and a method for manufacturing the micro light-emitting component matrix.

Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate and to provide probing structures (or pads). Testing structures, including daisy-chain structures, with metal lines to connect bonding structures connected to signals, power source, and/or grounding structures are connected to probing structures on the interconnect substrate. The testing structures enable determining the quality of bonding and/or functionalities of packaged dies bonded. After electrical testing is completed, the metal lines connecting the probing structures and the bonding structures are severed to allow proper function of devices in the die package. The mechanisms for forming test structures with probing pads on interconnect substrate and severing connecting metal lines after testing could reduce manufacturing cost.

A chip transfer method including: disposing a target substrate in a closed cavity, the target substrate including a first alignment bonding structure and a second alignment bonding structure; applying a charge of a first polarity to the first alignment bonding structure of the target substrate; applying a charge of a second polarity to a first chip bonding structure of a chip; injecting an insulating fluid into the closed cavity to suspend the chip in the insulating fluid within the closed cavity; and applying a bonding force to the chip.

A radio frequency module includes: a module board including first and second principal surfaces; first and second power amplifiers on the first principal surface; external-connection terminals on the second principal surface; and first and second via conductors connecting the first and second principal surfaces. The first and second via conductors are spaced apart in the module board, one end of the first via conductor is connected to a first ground electrode of the first power amplifier, the other end of the first via conductor is connected to a first external-connection terminal, one end of the second via conductor is connected to a second ground electrode of the second power amplifier, the other end of the second via conductor is connected to a second external-connection terminal, and the first and second via conductors each penetrate through the module board in a direction normal to the first and second principal surfaces.

An electrical conductor structure comprises a substrate and an electrical conductor disposed on or in the substrate. The electrical conductor comprises a first layer and a second layer disposed on a side of the first layer opposite the substrate. The first layer comprises a first electrical conductor that forms a non-conductive layer on a surface of the first electrical conductor when exposed to air and the second layer comprising a second electrical conductor that does not form a non-conductive layer on a surface of the second electrical conductor when exposed to air. A component comprises a connection post that is electrically connected to the second layer and the electrical conductor. The first and second layers can be inorganic. The first layer can comprise a metal such as aluminum and the second layer can comprise an electrically conductive metal oxide such as indium tin oxide.

A method of manufacturing a semiconductor device includes bonding a first semiconductor die and a second semiconductor die to a first substrate, forming a conductive layer over the first semiconductor die, the second semiconductor die, and the first substrate, applying an encapsulant over the conductive layer, and removing a portion of the encapsulant, wherein the removing the portion of the encapsulant exposes the conductive layer.