H01L2224/16505

Multi-chip package and manufacturing method thereof

A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a wiring structure and an interposer via electrically connected to the wiring structure; a plurality of semiconductor chips located on a first surface of the interposer and electrically connected to each other through the interposer; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface, wherein the plurality of semiconductor chips are electrically connected to the redistribution circuit structure through at least the interposer.

Semiconductor device with a heterogeneous solder joint and method for fabricating the same

A method for fabricating a semiconductor device with a heterogeneous solder joint includes: providing a semiconductor die; providing a coupled element; and soldering the semiconductor die to the coupled element with a first solder joint. The first solder joint includes: a solder material including a first metal composition; and a coating including a second metal composition, different from the first metal composition, the coating at least partially covering the solder material. The second metal composition has a greater stiffness and/or a higher melting point than the first metal composition.

Semiconductor device with a heterogeneous solder joint and method for fabricating the same

A method for fabricating a semiconductor device with a heterogeneous solder joint includes: providing a semiconductor die; providing a coupled element; and soldering the semiconductor die to the coupled element with a first solder joint. The first solder joint includes: a solder material including a first metal composition; and a coating including a second metal composition, different from the first metal composition, the coating at least partially covering the solder material. The second metal composition has a greater stiffness and/or a higher melting point than the first metal composition.

Radiation detector element

The present invention generally relates to a radiation detector element wherein a photodiode is transversely fixed to a detector element substrate through at least one connection comprising two fused solder balls, wherein a first of the two fused solder balls contacts the photodiode and a second of the two fused solder balls (contacts the detector element substrate. The invention further relates to a method of transversally attaching two substrates, in particular constructing the above-mentioned radiation detector element. It also relates to an imaging system comprising at least one radiation detector element.

Flexible printed circuit (FPC) board and method for manufacturing the same and OLED display device
11432404 · 2022-08-30 ·

A FPC board and a method for manufacturing the same and an OLED display device are provided. The FPC board includes a substrate, a first wire layer disposed on one side of the substrate, a circuit board terminal disposed at an edge on one side of the substrate and connected to the first wire layer, and a first protective layer covering the first wire layer. The thickness of the circuit board terminal is larger than the sum of the thicknesses of the first wire layer and the first protective layer. When the FPC board is connected to the OLED panel, one side of the base substrate on which the panel terminal is provided is opposite to one side of the substrate on which the circuit board terminal is provided, such that the base substrate overlaps with the substrate to connect the circuit board terminal and the panel terminal.

SOLDERLESS INTERCONNECT FOR SEMICONDUCTOR DEVICE ASSEMBLY
20210375822 · 2021-12-02 ·

Semiconductor device assemblies with solderless interconnects, and associated systems and methods are disclosed. In one embodiment, a semiconductor device assembly includes a first conductive pillar extending from a semiconductor die and a second conductive pillar extending from a substrate. The first conductive pillar may be connected to the second conductive pillar via an intermediary conductive structure formed between the first and second conductive pillars using an electroless plating solution injected therebetween. The first and second conductive pillars and the intermediary conductive structure may include copper as a common primary component, exclusive of an intermetallic compound (IMC) of a soldering process. A first sidewall surface of the first conductive pillar may be misaligned with respect to a corresponding second sidewall surface of the second conductive pillar. Such interconnects formed without IMC may improve electrical and metallurgical characteristics of the interconnects for the semiconductor device assemblies.

SOLDERLESS INTERCONNECT FOR SEMICONDUCTOR DEVICE ASSEMBLY
20210375822 · 2021-12-02 ·

Semiconductor device assemblies with solderless interconnects, and associated systems and methods are disclosed. In one embodiment, a semiconductor device assembly includes a first conductive pillar extending from a semiconductor die and a second conductive pillar extending from a substrate. The first conductive pillar may be connected to the second conductive pillar via an intermediary conductive structure formed between the first and second conductive pillars using an electroless plating solution injected therebetween. The first and second conductive pillars and the intermediary conductive structure may include copper as a common primary component, exclusive of an intermetallic compound (IMC) of a soldering process. A first sidewall surface of the first conductive pillar may be misaligned with respect to a corresponding second sidewall surface of the second conductive pillar. Such interconnects formed without IMC may improve electrical and metallurgical characteristics of the interconnects for the semiconductor device assemblies.

CLOSE BUTTED COLLOCATED VARIABLE TECHNOLOGY IMAGING ARRAYS ON A SINGLE ROIC
20220130883 · 2022-04-28 ·

A semiconductor-based imaging device and method of manufacture. A direct bond hybridization (DBH) structure is formed on a top surface of a read out integrated circuit (ROIC). A silicon-based detector is bonded to the ROIC via the DBH structure. A non-silicon-based detector is bonded to the DBH structure located on the top of the ROIC using indium-based hybridization.

SEMICONDUCTOR DEVICE WITH A HETEROGENEOUS SOLDER JOINT AND METHOD FOR FABRICATING THE SAME

A method for fabricating a semiconductor device with a heterogeneous solder joint includes: providing a semiconductor die; providing a coupled element; and soldering the semiconductor die to the coupled element with a first solder joint. The first solder joint includes: a solder material including a first metal composition; and a coating including a second metal composition, different from the first metal composition, the coating at least partially covering the solder material. The second metal composition has a greater stiffness and/or a higher melting point than the first metal composition.

SEMICONDUCTOR DEVICE WITH A HETEROGENEOUS SOLDER JOINT AND METHOD FOR FABRICATING THE SAME

A method for fabricating a semiconductor device with a heterogeneous solder joint includes: providing a semiconductor die; providing a coupled element; and soldering the semiconductor die to the coupled element with a first solder joint. The first solder joint includes: a solder material including a first metal composition; and a coating including a second metal composition, different from the first metal composition, the coating at least partially covering the solder material. The second metal composition has a greater stiffness and/or a higher melting point than the first metal composition.