Disclosed is a semiconductor package comprising a first semiconductor chip and at least one second semiconductor chip on the first semiconductor chip. The second semiconductor chip includes first and second test bumps that are adjacent to an edge of the second semiconductor chip and are on a bottom surface of the second semiconductor chip. The first and second test bumps are adjacent to each other. The second semiconductor chip also includes a plurality of data bumps that are adjacent to a center of the second semiconductor chip and are on the bottom surface of the second semiconductor chip. A first interval between the second test bump and one of the data bumps is greater than a second interval between the first test bump and the second test bump. The one of the data bumps is most adjacent to the second test bump.

Provided is a connection structure for a semiconductor package which includes: a first passivation layer having an opening; a first conductive pattern that penetrates the first passivation layer and protrudes upwardly from the first passivation layer; a second passivation layer on the first passivation layer and covering the first conductive pattern; a second conductive pattern on the second passivation layer and electrically connected to the first conductive pattern; a third passivation layer on the second passivation layer and covering the second conductive pattern; and an external terminal in the opening and electrically connected to the first conductive pattern, wherein the first conductive pattern is thicker than the second conductive pattern.

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a first bump and a first dummy bump between the chip and the substrate. The first bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, the first dummy bump is between the first bump and a corner of the chip, and the first dummy bump is wider than the first bump.

In one instance, a semiconductor package includes a metal leadframe having a first plurality of openings extending partially into the leadframe from the first side and a second plurality of openings extending partially into the leadframe from the second side together forming a plurality of leads. A pre-mold compound is positioned in the second plurality of openings that at least partially supports the plurality of leads. The semiconductor package has a plurality of bumps extending from the landing sites to a semiconductor die and a molding compounding at least partially covering the plurality of bumps and the metal leadframe. Other packages and methods are disclosed.

An exemplary semiconductor device can comprise (a) a substrate comprising a substrate dielectric structure between the substrate top side and the substrate bottom side, conductive pads at the substrate bottom side, and a substrate cavity through the substrate dielectric structure, (b) a base electronic component comprising inner short bumps; outer short bumps bounding a perimeter around the inner short bumps, and tall bumps between the outer short bumps and an edge of the base component top side, and (c) a mounted electronic component coupled to the inner short bumps of the base electronic component. The tall bumps of the base component can be coupled to the conductive pads of the substrate. The mounted electronic component can be located in the substrate cavity. The substrate bottom side can cover at least a portion of the outer short bumps of the base electronic component. Other examples and related methods are disclosed herein.

In one instance, a semiconductor package includes a metal leadframe having a first plurality of openings extending partially into the leadframe from the first side and a second plurality of openings extending partially into the leadframe from the second side together forming a plurality of leads. A pre-mold compound is positioned in the second plurality of openings that at least partially supports the plurality of leads. The semiconductor package has a plurality of bumps extending from the landing sites to a semiconductor die and a molding compounding at least partially covering the plurality of bumps and the metal leadframe. Other packages and methods are disclosed.

A method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first ring-like structure over a chip. The first ring-like structure surrounds the first conductive bump, the first ring-like structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring-like structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate through the first conductive bump.

A semiconductor device is disclosed including a semiconductor die mounted on a substrate. The substrate includes a pattern of solder balls which is complementary and aligned to a pattern of solder bumps on the semiconductor die. These complementary and aligned patterns of solder balls and solder bumps minimize the lengths of current paths between the solder balls and solder bumps, and provide current paths between the solder balls and solder bumps of relatively uniform lengths.

A semiconductor package may comprise: a first passivation layer forming an electrical connection with one or more first bumps; a substrate layer including a second passivation layer and a silicon layer; a back-end-of-line (BEOL) layer formed on the substrate layer; and a third passivation layer formed on the BEOL layer forming an electrical connection with one or more second bumps, wherein the substrate layer includes a first signal TSV (Through Silicon Via) which transmits a first signal between the BEOL layer and a first lower pad, a second signal TSV which transmits a second signal between the BEOL layer and a second lower pad, and a ground TSV which is disposed between the first signal TSV and the second signal TSV and formed so that one end thereof is connected to the BEOL layer and the other end thereof floats.

The present disclosure relates to evaluation of a mounted resistor formed between a bump and electrodes. A display device of the present disclosure includes a display panel formed in a transparent substrate and a display driver driving the display panel. A plurality of bumps is formed on a connection surface of the display driver. A plurality of electrodes is formed on the transparent substrate and corresponds in position to the plurality of bumps. COG mounting enables the bumps on the display driver side to electrically connect to the electrodes on the transparent substrate side. On the connection surface of the display driver, the bumps, which are for use in signal transmission, further include a first evaluation-oriented bump (TA[i]) and a second evaluation-oriented bump (TB[i]). Evaluation-oriented electrodes (EL[i]) are disposed on the transparent substrate and correspond in position to the first evaluation-oriented bump (TA[i]) and the second evaluation-oriented bump (TB[i]). Upon completion of COG mounting, a resistance value evaluation circuit (140a) disposed on the display driver generates evaluation signal (DET[i]) corresponding to resistance value (RA[i]+RB[i]) between the evaluation-oriented electrodes and the first and second evaluation-oriented bumps.