A semiconductor device may include a bond pad/probe pad pair that includes a bond pad and a probe pad positioned to be adjacent to each other to form an L shape. The device may also include a through-silicon via (TSV) pad positioned to be at least partially or entirely inside the recess area of the L shape. The bond pad and the probe pad may each have an opening, and at least a portion of the opening of the bond pad may extend into a portion of the opening of the probe pad. The arrangement of the bond pad, the probe pad and the TSV may be implemented in a wafer-on-wafer (WOW) that includes multiple stacked wafers. A method of fabricating the TSV may include etching the stacked wafers to form a TSV opening that extends through the multiple wafers, and filling the TSV opening with conductive material.

An electronic assembly comprising a carrier wafer having a top wafer surface and a bottom wafer surface; an electronic integrated circuit being formed in the carrier wafer and comprising an integrated circuit contact pad on the top wafer surface; said carrier wafer comprising a through-wafer cavity having walls that join said top wafer surface to said bottom wafer surface; a component chip having a component chip top surface, a component chip bottom surface and component chip side surfaces, the component chip being held in said through-wafer cavity by direct contact of at least a side surface of said component chip with an attachment metal that fills at least a portion of said through-wafer cavity; said component chip comprising at least one component contact pad on said component chip bottom surface; and a conductor connecting said integrated circuit contact pad and said component contact pad.

Various embodiments include a method for producing a least one conductive track comprising: forming a surface with a thermoplastic; and depositing conductive track material on the surface by thermal spraying.

A light-emitting apparatus includes a substrate, pads disposed on the substrate, a sacrificial pattern layer and a light-emitting diode element disposed on the sacrificial pattern layer. The light-emitting diode element includes a first type semiconductor layer, a second type semiconductor layer, an active layer, and electrodes. A connection patterns disposed on at least one of the electrodes and the pads. Materials of the connection patterns include hot fluidity conductive materials. The connection patterns cover an outermost sidewall of the sacrificial pattern layer and are electrically connected to the at least one of the electrodes and the pads. The sacrificial pattern layer is located between the connection patterns, and the sacrificial pattern layer is overlapped with the pads in a normal direction of the substrate.

A display device comprising: a first substrate; a plurality of pixels provided to the first substrate; a light emitting element provided to each of the pixels; a phosphor layer covering at least an upper surface of the light emitting element; a first reflective layer facing a side surface of the light emitting element; and a second reflective layer provided to a side surface of the phosphor layer, separated from the first reflective layer in a normal direction of the first substrate, and disposed farther away from the first substrate than the first reflective layer.

A display driver integrated circuit (IC) device includes a first substrate having a first front surface and a first back surface; a first interlayer insulating layer on the first front surface; a wiring layer in the first interlayer insulating layer; a first bonding insulating layer on the first interlayer insulating layer; a second substrate having a second front surface and a second back surface, the second front surface being disposed toward the first front surface; a second interlayer insulating layer on the second front surface a second bonding insulating layer on the second interlayer insulating layer and physically bonded to the first bonding insulating layer; and a back via stack structure penetrating the second substrate, the second interlayer insulating layer, the second bonding insulating layer, the first bonding insulating layer, and the first interlayer insulating layer and electrically connected to the wiring layer.

A light-emitting apparatus includes a substrate, pads disposed on the substrate, a sacrificial pattern layer and a light-emitting diode element disposed on the sacrificial pattern layer. The light-emitting diode element includes a first type semiconductor layer, a second type semiconductor layer, an active layer, and electrodes. A connection patterns disposed on at least one of the electrodes and the pads. Materials of the connection patterns include hot fluidity conductive materials. The connection patterns cover a sidewall of the sacrificial pattern layer and are electrically connected to the at least one of the electrodes and the pads. In addition, the manufacturing method of the above light-emitting apparatus is also proposed.

The present technology relates to a semiconductor package. The semiconductor package comprises: a first component comprising a plurality of first dies stacked on top of each other, each of first dies comprising at least one side surface and an electrical contact exposed on the side surface, and the plurality of first dies aligned so that the corresponding side surfaces of all first dies substantially coplanar with respect to each other to form a common sidewall; a first conductive pattern formed over the sidewall and at least partially spaced away from the sidewall, the first conductive pattern electrically interconnecting the electrical contacts of the plurality of first dies; at least one second component; and a second conductive pattern formed on a surface of the second component, the second conductive pattern affixed and electrically connected to the first conductive pattern formed over the sidewall of the first component.

A display driver integrated circuit (IC) device includes a first substrate having a first front surface and a first back surface; a first interlayer insulating layer on the first front surface; a wiring layer in the first interlayer insulating layer; a first bonding insulating layer on the first interlayer insulating layer; a second substrate having a second front surface and a second back surface, the second front surface being disposed toward the first front surface; a second interlayer insulating layer on the second front surface a second bonding insulating layer on the second interlayer insulating layer and physically bonded to the first bonding insulating layer; and a back via stack structure penetrating the second substrate, the second interlayer insulating layer, the second bonding insulating layer, the first bonding insulating layer, and the first interlayer insulating layer and electrically connected to the wiring layer.

An electronic assembly, comprising a carrier wafer having a top wafer surface and a bottom wafer surface; an electronic integrated circuit being formed in the carrier wafer and comprising a wafer contact pad on the top wafer surface; said carrier wafer comprising a through-wafer cavity joining the top and bottom wafer surfaces; a component chip having a component chip top surface, a component chip bottom surface and component chip side surfaces, the component chip being held in said through-wafer cavity by direct contact of at least a side surface of said first component chip with an attachment metal that fills at least a portion of said through-wafer cavity; said component chip comprising at least one component contact pad on said component chip top surface; a first conductor connecting said wafer contact pad and said component contact pad.