A device chip for mounting on a board is provided. The device chip includes a top surface, an undersurface located on an opposite side from the top surface and having a larger area than the top surface, a slope inclined with respect to the top surface and the undersurface and exposed to the top surface side, a circuit portion on the top surface side, the circuit portion including an electronic circuit, and a wiring portion on which wiring electrically connecting the circuit portion and the board to each other is to be formed, the wiring portion including the slope in a part of the wiring portion.

A display device may include a first scan line, a first data line and a second data line, a first read-out line and a second read-out line. A first sub-pixel may be connected to the first scan line, the first data line, and the first read-out line. A second sub-pixel may be connected to the first scan line, the first data line, and the second read-out line. A third sub-pixel may be connected to the first scan line, the second data line, and the first read-out line. Each of the first sub-pixel, the second sub-pixel, and the third sub-pixel may include at least one light emitting element.

A wafer-level system-in-package (WLSiP) package structure is provided. The WLSiP package structure includes a device wafer, an adhesive layer, and a plurality of second chips. The device wafer includes a first front surface having a plurality of first chips integrated therein and a first back surface opposing the first front surface. The adhesive layer is formed on the first front surface of the device wafer and the adhesive layer includes a plurality of through-holes exposing the first front surface. The plurality of second chips are bonded to the device wafer, and the plurality of second chips are bonded with the adhesive layer to cover the plurality of first through-holes in a one-to-one correspondence.

A memory device, a semiconductor device and their manufacturing methods are provided. One of the methods may include: providing a first die and a plurality of second dies, the first die having a first pad, each of the plurality of second dies having a second pad; stacking the plurality of second dies on the first die, the second pads and the first pad arranged in a stepwise manner, and projections of the second pads of any two adjacent second dies on the first die partially overlapped; forming a connecting hole passing through the second dies; and forming a conductive body filling the connecting hole and connecting the first pad and the second pads. This method simplifies the manufacturing process of a semiconductor device, reduces the cost thereof, and improves the production yield.

Wafer-level packaging structure is provided. First chips are bonded to the device wafer. A first encapsulation layer is formed on the device wafer, covering the first chips. The first chip includes: a chip front surface with a formed first pad, facing the device wafer; and a chip back surface opposite to the chip front surface. A first opening is formed in the first encapsulation layer to expose at least one first chip having an exposed chip back surface for receiving a loading signal. A metal layer structure is formed covering the at least one first chip, a bottom and sidewalls of the first opening, and the first encapsulation layer, followed by an alloying treatment on the chip back surface and the metal layer structure to form a back metal layer on the chip back surface.

A light emitting element, a light emitting device and a manufacturing method thereof are provided. The manufacturing method of the light emitting device includes forming a first electrode and a second electrode spaced apart from each other on a substrate on which the light emitting area is defined; injecting a solution including a light emitting element and a liquid crystal molecule into the light emitting area; and aligning the light emitting element such that the first electrode and the second electrode are electrically coupled; wherein the light emitting element includes a first semiconductor layer; a second semiconductor layer; an active layer interposed between the first semiconductor layer and the second semiconductor layer; an insulation layer formed to surround an outer surface of the active layer; and an organic ligand layer formed on an outer surface of the insulating layer.

Semiconductor device packages may include a first semiconductor device over a substrate and a second semiconductor device over the first semiconductor device. An active surface of the second semiconductor device may face away from the substrate. Electrical interconnections may extend from bond pads of the second semiconductor device, along surfaces of the second semiconductor device, first semiconductor device, and substrate to pads of routing members of the substrate. The electrical interconnections may include conductors in contact with the bond pads and the routing members and a dielectric material interposed between the conductors and the first semiconductor device, the second semiconductor device and the substrate between the bond pads and the pad of the routing members. An encapsulant distinct from the dielectric material may cover the electrical interconnections, the first semiconductor device, the second semiconductor device, and an upper surface of the substrate. Methods of fabrication are also disclosed.

A chip package includes a semiconductor substrate, a supporting element, an antenna layer, and a redistribution layer. The semiconductor substrate has an inclined sidewall and a conductive pad that protrudes from the inclined sidewall. The supporting element is located on the semiconductor substrate, and has a top surface facing away from the semiconductor substrate, and has an inclined sidewall adjoining the top surface. The antenna layer is located on the top surface of the supporting element. The redistribution layer is located on the inclined sidewall of the supporting element, and is in contact with a sidewall of the conductive pad and an end of the antenna.

A device chip for mounting on a board is provided. The device chip includes a top surface, an undersurface located on an opposite side from the top surface and having a larger area than the top surface, a slope inclined with respect to the top surface and the undersurface and exposed to the top surface side, a circuit portion on the top surface side, the circuit portion including an electronic circuit, and a wiring portion on which wiring electrically connecting the circuit portion and the board to each other is to be formed, the wiring portion including the slope in a part of the wiring portion.

A display device according to one or more embodiments of the present disclosure includes a substrate, a first electrode and a second electrode on the substrate, a light emitting element electrically connected to the first electrode and the second electrode, and a first reflective layer on the light emitting element and including an opening overlapping the light emitting element, wherein the first reflective layer includes a material having a first reflectivity.