A semiconductor package system includes a substrate, a first and a second semiconductor package, a first thermal conductive layer, a first passive device, and a heat radiation structure. The first and second semiconductor package and first passive device may be mounted on a top surface of the substrate. The first semiconductor package may include a first semiconductor chip that includes a plurality of logic circuits. The first thermal conductive layer may be on the first semiconductor package. The heat radiation structure may be on the first thermal conductive layer, the second semiconductor package, and the first passive device. The heat radiation structure may include a first bottom surface physically contacting the first thermal conductive layer, and a second bottom surface at a higher level than that of the first bottom surface. The second bottom surface may be on the second semiconductor package and/or the first passive device.

Provided is a semiconductor package system. The system includes a substrate, a first semiconductor package on the substrate, a second semiconductor package on the substrate, a first passive element on the substrate, a heat dissipation structure on the first semiconductor package, the second semiconductor package, and the first passive element, and a first heat conduction layer between the first semiconductor package and the heat dissipation structure. A sum of a height of the first semiconductor package and a thickness of the first heat conduction layer may be greater than a height of the first passive element. The height of the first semiconductor package may be greater than a height of the second semiconductor package.

Provided is a semiconductor package system. The system includes a substrate, a first semiconductor package on the substrate, a second semiconductor package on the substrate, a first passive element on the substrate, a heat dissipation structure on the first semiconductor package, the second semiconductor package, and the first passive element, and a first heat conduction layer between the first semiconductor package and the heat dissipation structure. A sum of a height of the first semiconductor package and a thickness of the first heat conduction layer may be greater than a height of the first passive element. The height of the first semiconductor package may be greater than a height of the second semiconductor package.

A method for manufacturing a module including N layers of stacked resin is provided, wherein N is a natural number of two or more. In the method, resin of a first layer is cured to a degree that does not fully harden the resin of the first layer. Resin of a Mth layer is stacked on resin of a (M1)th layer, wherein M is a natural number of two or more and less than N. The resin of the Mth layer is cured to a degree that does not fully harden the resin of the Mth layer. Stacking the resin of the Mth layer and curing the resin of the Mth layer are repeated. Then, resin of Nth layer is stacked, and all of the N layers of stacked resin are fully hardened.

A hybrid bonding layer includes a metal inverse opal (MIO) layer with a plurality of hollow spheres and a predefined porosity, and a ball grid array (BGA) disposed within the MIO layer. The MIO layer and the BGA may be disposed between a pair of bonding layers. The MIO layer and the BGA each have a melting point above a TLP sintering temperature and the pair of bonding layers each have a melting point below the TLP sintering temperature such that the hybrid bonding layer can be transient liquid phase bonded between a substrate and a semiconductor device. The pair of bonding layers may include a first pair of bonding layers with a melting point above the TLP sintering temperature and a second pair of bonding layers with a melting point below the TLP sintering temperature.

The present invention provides an anisotropic electrically conductive film with a structure, in which electrically conductive particles are disposed at lattice points of a planar lattice pattern in an electrically insulating adhesive base layer. A proportion of the lattice points, at which no electrically conductive particle is disposed, with respect to all the lattice points of the planar lattice pattern assumed as a reference region, is less than 20%. A proportion of the lattice points, at which plural electrically conductive particles are disposed in an aggregated state, with respect to all the lattice points of the planar lattice pattern, is not greater than 15%. A sum of omission of the electrically conductive particle and an aggregation of the electrically conductive particles is less than 25%.

A hybrid bonding layer includes a metal inverse opal (MIO) layer with a plurality of hollow spheres and a predefined porosity, and a ball grid array (BGA) disposed within the MIO layer. The MIO layer and the BGA may be disposed between a pair of bonding layers. The MIO layer and the BGA each have a melting point above a TLP sintering temperature and the pair of bonding layers each have a melting point below the TLP sintering temperature such that the hybrid bonding layer can be transient liquid phase bonded between a substrate and a semiconductor device. The pair of bonding layers may include a first pair of bonding layers with a melting point above the TLP sintering temperature and a second pair of bonding layers with a melting point below the TLP sintering temperature.

The present invention provides an anisotropic electrically conductive film with a structure, in which electrically conductive particles are disposed at lattice points of a planar lattice pattern in an electrically insulating adhesive base layer. A proportion of the lattice points, at which no electrically conductive particle is disposed, with respect to all the lattice points of the planar lattice pattern assumed as a reference region, is less than 20%. A proportion of the lattice points, at which plural electrically conductive particles are disposed in an aggregated state, with respect to all the lattice points of the planar lattice pattern, is not greater than 15%. A sum of omission of the electrically conductive particle and an aggregation of the electrically conductive particles is less than 25%.

A first electronic element is disclosed, which includes: a first substrate having a first surface; a first electrode pad disposed on the first surface, wherein the first electrode pad has a second surface away from the first substrate; and an insulating layer disposed on the first surface, wherein the insulating layer includes an opening, the opening is disposed correspondingly to the first electrode pad, and the opening overlaps the first electrode pad in a normal direction of the first surface, wherein the insulating layer has a third surface away from the first substrate, a distance between the third surface and the second surface in the normal direction of the first surface is defined as a first distance, and the first distance is greater than 0 m and less than or equal to 14 m. In addition, the disclosure further provides an electronic device including the first electronic element.

A method for joining an electronic part, comprising: inserting a joining silver sheet between an electronic part and a substrate, to which the electronic part is to be joined; and heating them to the temperature range of T.sub.A ( C.) or higher and T.sub.B ( C.) or lower, under application of a pressure to the electronic part and the substrate to make a contact surface pressure of the electronic part and the silver sheet of from 0.5 to 3 MPa. The joining silver sheet comprises silver particles having a particle diameter of from 1 to 250 nm integrated by sintering, and has a capability of further undergoing sintering on heating and retaining the silver sheet at a temperature range of T.sub.A ( C.) or higher and T.sub.B ( C.) or lower satisfying the following expression (1): 270T.sub.A<T.sub.B350.