A semiconductor chip including a semiconductor substrate having a first surface and a second surface and having an active layer in a region adjacent to the first surface, a first through electrode penetrating at least a portion of the semiconductor substrate and connected to the active layer, a second through electrode located at a greater radial location from the center of the semiconductor substrate than the first through electrode, penetrating at least a portion of the semiconductor substrate, and connected to the active layer. The semiconductor chip also including a first chip connection pad having a first height and a first width, located on the second surface of the semiconductor substrate, and connected to the first through electrode, and a second chip connection pad having a second height greater than the first height and a second width greater than the first width, located on the second surface of the semiconductor substrate, and connected to the second through electrode.

A first anisotropic conductive film 1A or a second anisotropic conductive film 1B has a first insulating resin layer 2 and a second insulating resin layer 3. The first insulating resin layer 2 is formed of a photopolymerized resin, and the second insulating resin layer 3 is formed of a polymerizable resin. Conductive particles 10 are disposed in a single layer on a surface of the first insulating resin layer 2 on a side of the second insulating resin layer 3. The first anisotropic conductive film further has a third insulating resin layer 4 formed of a polymerizable resin, and the second anisotropic conductive film 1B has an intermediate insulating resin layer 6. The intermediate insulating resin layer 6 is formed of a resin containing no polymerization initiator, and is in contact with the conductive particles 10. These anisotropic conductive films have favorable connection reliability.

The invention relates to display device and method of manufacturing the same. The display device includes: a substrate; a driving pad disposed on the substrate; an insulating layer exposing the driving pad and disposed on the substrate; a circuit board including a circuit pad overlapping the driving pad; and a connector disposed between the circuit board and the insulating layer and including a plurality of conductive particles electrically connecting the driving pad and the circuit pad, the driving pad including: a first pad disposed on the substrate; and a second pad disposed on the first pad and having an opening exposing the first pad.

A semiconductor package includes a base chip and at least one semiconductor chip disposed on the base chip. An adhesive film is disposed between the base chip and the at least one semiconductor chip and is configured to fix the at least one semiconductor chip on the base chip. The adhesive film includes an inner film portion that overlaps the at least one semiconductor chip in a thickness direction of the base chip, and an outer film portion that does not overlap the at least one semiconductor chip in the thickness direction of the base chip. A width of the outer film portion in a direction perpendicular to a lateral edge of the at least one semiconductor chip is substantially uniform within a deviation range of 20% of an average width of the outer film portion.

An electronic device includes: a first semiconductor die having a metal region; a substrate having a plurality of metal regions; a first soldered joint between the metal region of the first semiconductor die and a first metal region of the substrate, the first soldered joint having one or more intermetallic phases throughout the entire soldered joint, each of the one or more intermetallic phases formed from a solder preform diffused into the metal region of the first semiconductor die and the first metal region of the substrate; and a second semiconductor die soldered to the first or different metal region of the substrate.

A semiconductor package includes a base chip and at least one semiconductor chip disposed on the base chip. An adhesive film is disposed between the base chip and the at least one semiconductor chip and is configured to fix the at least one semiconductor chip on the base chip. The adhesive film includes an inner film portion that overlaps the at least one semiconductor chip in a thickness direction of the base chip, and an outer film portion that does not overlap the at least one semiconductor chip in the thickness direction of the base chip. A width of the outer film portion in a direction perpendicular to a lateral edge of the at least one semiconductor chip is substantially uniform within a deviation range of 20% of an average width of the outer film portion.

This member connection method includes: a cutting step of forming cutting lines C in an adhesive layer at predetermined intervals at least in a width direction of an adhesive tape and making segments of the adhesive layer divided by the cutting lines C continuous at least in a lengthwise direction of the adhesive tape; a transfer step of disposing the segments to face a connection surface of one member to be connected, pressing a heating and pressing tool having an arbitrary pattern shape against the adhesive tape from a separator side and selectively transferring the segments to the one member to be connected; and a connection step for connecting another member to be connected to the one member to be connected via the segments transferred to the one member to be connected.

This member connection method includes: a cutting step of forming cutting lines C in an adhesive layer at predetermined intervals at least in a width direction of an adhesive tape and making segments of the adhesive layer divided by the cutting lines C continuous at least in a lengthwise direction of the adhesive tape; a transfer step of disposing the segments to face a connection surface of one member to be connected, pressing a heating and pressing tool having an arbitrary pattern shape against the adhesive tape from a separator side and selectively transferring the segments to the one member to be connected; and a connection step for connecting another member to be connected to the one member to be connected via the segments transferred to the one member to be connected.

A semiconductor chip including a semiconductor substrate having a first surface and a second surface and having an active layer in a region adjacent to the first surface, a first through electrode penetrating at least a portion of the semiconductor substrate and connected to the active layer, a second through electrode located at a greater radial location from the center of the semiconductor substrate than the first through electrode, penetrating at least a portion of the semiconductor substrate, and connected to the active layer. The semiconductor chip also including a first chip connection pad having a first height and a first width, located on the second surface of the semiconductor substrate, and connected to the first through electrode, and a second chip connection pad having a second height greater than the first height and a second width greater than the first width, located on the second surface of the semiconductor substrate, and connected to the second through electrode.

Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package is provided that includes a fan-out redistribution layer (RDL) structure that has plural stacked polymer layers, plural metallization layers, plural conductive vias interconnecting adjacent metallization layers of the metallization layers, and plural rivets configured to resist delamination of one or more of the polymer layers. Each of the plural rivets includes a first head, a second head and a shank connected between the first head and the second head. The first head is part of one of the metallization layers. The shank includes at least one of the conductive vias and at least one part of another of the metallization layers.