Patent classifications
H01L2224/27422
Engineered Polymer-Based Electronic Materials
A composition for use in an electronic assembly process, the composition comprising a filler dispersed in an organic medium, wherein: the organic medium comprises a polymer; the filler comprises one or more of graphene, functionalized graphene, graphene oxide, a polyhedral oligomeric silsesquioxane, graphite, a 2D material, aluminum oxide, zinc oxide, aluminum nitride, boron nitride, silver, nano fibers, carbon fibers, diamond, carbon nanotubes, silicon dioxide and metal-coated particles, and the composition comprises from 0.001 to 40 wt. % of the filler based on the total weight of the composition.
Reactive hot-melt adhesive for use on electronics
The disclosure relates to a method of making an electronic assembly with a reactive hot-melt adhesive composition that include an atmospheric curing prepolymer and optionally a thermoplastic component with a softening point of at least about 120 C., and the electronic assembly made therewith.
Reactive hot-melt adhesive for use on electronics
The disclosure relates to a method of making an electronic assembly with a reactive hot-melt adhesive composition that include an atmospheric curing prepolymer and optionally a thermoplastic component with a softening point of at least about 120 C., and the electronic assembly made therewith.
Integrated circuit package and method of making same
A chip package includes a first die with an active surface having at least one die pad positioned thereon; a first adhesive layer having a first surface coupled to the active surface of the first die and a second surface opposite the first surface; and a first dielectric layer having a top surface. A first portion of the top surface of the first dielectric layer is coupled to the second surface of the first adhesive layer. A second portion of the top surface of the first dielectric layer, distinct from the first portion, is substantially free of adhesive.
Integrated circuit package and method of making same
A chip package includes a first die with an active surface having at least one die pad positioned thereon; a first adhesive layer having a first surface coupled to the active surface of the first die and a second surface opposite the first surface; and a first dielectric layer having a top surface. A first portion of the top surface of the first dielectric layer is coupled to the second surface of the first adhesive layer. A second portion of the top surface of the first dielectric layer, distinct from the first portion, is substantially free of adhesive.