A method for manufacturing an electronic component package. The method includes (i) providing a package precursor in which an electronic component is embedded such that an electrode of the electronic component is exposed at a surface of a sealing resin layer; (ii) forming a first metal plating layer such that the first metal plating layer is in contact with the exposed surface of the electrode of the electronic component; (iii) disposing a metal foil in face-to-face spaced relationship with respect to the first metal plating layer; and (iv) forming a second metal plating layer. In step (iv), the second metal plating layer is formed so as to fill a clearance between the first metal plating layer and the metal foil, thereby integrating the metal foil, the first metal plating layer and the second metal plating layer with each other.

A semiconductor device includes a semiconductor substrate with a wiring layer formed thereon, an insulating film formed on the semiconductor substrate so as to cover the wiring layer and having a pad opening exposing a portion of the wiring layer as a pad, a front surface protection film formed on the insulating film and being constituted of an insulating material differing from the insulating film and having a second pad opening securing exposure of at least a portion of the pad, a seed layer formed on the pad, and a plating layer formed on the seed layer.

The present invention relates to a method of forming a joint bonding together two solid objects and joints made by the method, where the joint is formed by a layer of a binary system which upon heat treatment forms a porous, coherent and continuous single solid-solution phase extending across a bonding layer of the joint.

The present invention relates to a method of forming a joint bonding together two solid objects and joints made by the method, where the joint is formed by a layer of a binary system which upon heat treatment forms a porous, coherent and continuous single solid-solution phase extending across a bonding layer of the joint.

A device (2) is formed on a main surface of a substrate (1). The main surface of the substrate (1) is bonded to the undersurface of the counter substrate (14) via the bonding member (11,12,13) in a hollow state. A circuit (17) and a bump structure (26) are formed on the top surface of the counter substrate (14). The bump structure (26) is positioned in a region corresponding to at least the bonding member (11,12,13), and has a higher height than that of the circuit (17).

A device (2) is formed on a main surface of a substrate (1). The main surface of the substrate (1) is bonded to the undersurface of the counter substrate (14) via the bonding member (11,12,13) in a hollow state. A circuit (17) and a bump structure (26) are formed on the top surface of the counter substrate (14). The bump structure (26) is positioned in a region corresponding to at least the bonding member (11,12,13), and has a higher height than that of the circuit (17).

A solid-state amplifier architecture is disclosed. In some embodiments, the disclosed architecture may include first and second channel chipsets configured to amplify either the entire instantaneous frequency band of a radio frequency (RF) input signal or, respectively, sub-bands thereof, which may be divided proportionally between the two chipsets. In some cases, the chipsets may be configured to amplify frequencies in excess of the entire K-band and K.sub.a-band frequencies simultaneously. In some cases, the architecture may be configured to address a signal received, for instance, from an electronic warfare (EW) system to a log amplifier stage configured to output a signal to the EW system, in response to which the EW system may generate a RF signal for amplification by the architecture for transmission. To facilitate heat dissipation, the architecture may be coupled, in part or in whole, with a thermally conductive carrier, optionally with an intervening diamond heat spreader layer.

A semiconductor device includes a solder supporting material above a substrate. The semiconductor device also includes a solder on the solder supporting material. The semiconductor device further includes selective laser annealed or laser ablated portions of the solder and underlying solder supporting material to form a semiconductor device having 3D features.

A semiconductor device includes a solder supporting material above a substrate. The semiconductor device also includes a solder on the solder supporting material. The semiconductor device further includes selective laser annealed or laser ablated portions of the solder and underlying solder supporting material to form a semiconductor device having 3D features.

A semiconductor wafer stack and a method of forming a semiconductor device is disclosed. The method includes providing a wafer stack with first and second wafers bonded together. The wafers include edge and non-edge regions, and at least one of the first and second wafers includes devices formed in the non-edge region. The first wafer serves as the base wafer while the second wafer serves as the top wafer of the wafer stack, where the base wafer is wider than the top wafer, providing a step edge of the wafer stack. An edge protection seal is formed on the wafer stack, where first and second layers are deposited on the wafer stack including at the top wafer and step edge of the wafer stack. The portion of the first and second layers on the step edge of the wafer stack forms the edge protection seal which protects the devices in the wafer stack in subsequent processing.