A three-dimensional stacking technique performed in a wafer-to-wafer fashion reducing the machine movement in production. The wafers are processed with metallic traces and stacked before dicing into separate die stacks. The traces of each layer of the stacks are interconnected via electroless plating.

A method of forming a solar cell device that includes forming a porous layer in a monocrystalline donor substrate and forming an epitaxial semiconductor layer on the porous layer. A solar cell structure is formed on the epitaxial semiconductor layer. A carrier substrate is bonded to the solar cell structure through a bonding layer. The monocrystalline donor substrate is removed by cleaving the porous layer. A grid of metal contacts is formed on the epitaxial semiconductor layer. The exposed portions of the epitaxial semiconductor layer are removed. The exposed surface of the solar cell structure is textured. The textured surface may be passivated, in which the passivated surface can provide an anti-reflective coating.

A method of forming a solar cell device that includes forming a porous layer in a monocrystalline donor substrate and forming an epitaxial semiconductor layer on the porous layer. A solar cell structure is formed on the epitaxial semiconductor layer. A carrier substrate is bonded to the solar cell structure through a bonding layer. The monocrystalline donor substrate is removed by cleaving the porous layer. A grid of metal contacts is formed on the epitaxial semiconductor layer. The exposed portions of the epitaxial semiconductor layer are removed. The exposed surface of the solar cell structure is textured. The textured surface may be passivated, in which the passivated surface can provide an anti-reflective coating.

A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.

An anisotropic electrically conductive film includes electrically conductive particles disposed in an electrically insulating adhesive layer. The particles are arranged at a predetermined pitch along first axes, arranged side by side, and are substantially spherical. The particle pitch at the first axes and the axis pitch of the first axes are both greater than or equal to 1.5D, D being an average particle diameter of the particles. Directions of all sides of a triangle formed by a particle (P0), which is one of the electrically conductive particles at one of the first axes, an electrically conductive particle (P1), which is at the one of the first axes and adjacent to the particle (P0), and an electrically conductive particle (P2), which is at another one of the first axes that is adjacent to the one of the first axes, are oblique to a film width direction of the conductive film.

A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.

A multilayer composite bonding material for transient liquid phase bonding a semiconductor device to a metal substrate includes thermal stress compensation layers sandwiched between a pair of bonding layers. The thermal stress compensation layers may include a core layer with a first stiffness sandwiched between a pair of outer layers with a second stiffness that is different than the first stiffness such that a graded stiffness extends across a thickness of the thermal stress compensation layers. The thermal stress compensation layers have a melting point above a sintering temperature and the bonding layers have a melting point below the sintering temperature. The graded stiffness across the thickness of the thermal stress compensation layers compensates for thermal contraction mismatch between the semiconductor device and the metal substrate during cooling from the sintering temperature to ambient temperature.

A semiconductor device according to the present invention includes: a substrate; a heat generating portion provided on the substrate; a cap substrate provided above the substrate so that a hollow portion is provided between the substrate and the cap substrate; and a reflection film provided above the heat generating portion and reflecting a medium wavelength infrared ray. The reflection film reflects the infrared ray radiated to the cap substrate side through the hollow portion due to the temperature increase of the heat generating portion, so that the temperature increase of the cap substrate side can be suppressed. Because of this function, even if mold resin is provided on the cap substrate, increase of the temperature of the mold resin can be suppressed.

A semiconductor device according to the present invention includes: a substrate; a heat generating portion provided on the substrate; a cap substrate provided above the substrate so that a hollow portion is provided between the substrate and the cap substrate; and a reflection film provided above the heat generating portion and reflecting a medium wavelength infrared ray. The reflection film reflects the infrared ray radiated to the cap substrate side through the hollow portion due to the temperature increase of the heat generating portion, so that the temperature increase of the cap substrate side can be suppressed. Because of this function, even if mold resin is provided on the cap substrate, increase of the temperature of the mold resin can be suppressed.

A nanowire bonding interconnect for fine-pitch microelectronics is provided. Vertical nanowires created on conductive pads provide a debris-tolerant bonding layer for making direct metal bonds between opposing pads or vias. Nanowires may be grown from a nanoporous medium with a height between 200-1000 nanometers and a height-to-diameter aspect ratio that enables the nanowires to partially collapse against the opposing conductive pads, creating contact pressure for nanowires to direct-bond to opposing pads. Nanowires may have diameters less than 200 nanometers and spacing less than 1 m from each other to enable contact or direct-bonding between pads and vias with diameters under 5 m at very fine pitch. The nanowire bonding interconnects may be used with or without tinning, solders, or adhesives. A nanowire forming technique creates a nanoporous layer on conductive pads, creates nanowires within pores of the nanoporous layer, and removes at least part of the nanoporous layer to reveal a layer of nanowires less than 1 m in height for direct bonding.