Structures and methods of fabricating semiconductor wafer assemblies that encapsulate one or die in a cavity etched into an oxide bonded semiconductor wafer stack. The methods generally include the steps of positioning the die in the cavity, mechanically and electrically mounting the die to the wafer stack, and encapsulating the die within the cavity by bonding a lid wafer to the wafer stack in one of multiple ways. Semiconductor processing steps are applied to construct the assemblies (e.g., deposition, annealing, chemical and mechanical polishing, etching, etc.) and connecting the die (e.g., bump bonding, wire interconnecting, ultrasonic bonding, oxide bonding, etc.) according to the embodiments described above.

A light-emitting device includes a carrier, a light-emitting element and a connection structure. The carrier includes a first electrical conduction portion. The light-emitting element includes a first light-emitting layer capable of emitting first light and a first contact electrode formed under the light-emitting layer. The first contact electrode is corresponded to the first electrical conduction portion. The connection structure includes a first electrical connection portion and a protective portion surrounding the first contact electrode and the first electrical connection portion. The first electrical connection portion includes an upper portion, a lower portion and a neck portion arranged between the upper portion and the lower portion. An edge of the upper portion is protruded beyond the neck portion, and an edge of the lower portion is protruded beyond the upper portion.

A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise a sensing area on a bottom side of a die without top side electrodes that senses fingerprints from the top side, and/or that comprise a sensor die directly electrically connected to conductive elements of a plate through which fingerprints are sensed.

In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.

In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.

A package structure and method of manufacturing is provided, whereby a bonding dielectric material layer is provided at a back side of a wafer, a bonding dielectric material layer is provided at a front side of an adjoining wafer, and wherein the bonding dielectric material layers are fusion bonded to each other.

A multi-layer preform sheet having at least a first layer and a second layer, the first layer being composed of a solder material that contains an intermetallic compound, and the second layer containing a first metal having a melting point of 300 C. or above, and a second metal capable of forming an intermetallic compound with the first metal.

A power module substrate with a Ag underlayer of the invention includes: a circuit layer that is formed on one surface of an insulating layer; and a Ag underlayer that is formed on the circuit layer, in which the Ag underlayer is composed of a glass layer that is formed on the circuit layer side and a Ag layer that is formed by lamination on the glass layer, and regarding the Ag underlayer, in a Raman spectrum obtained by a Raman spectroscopy with incident light made incident from a surface of the Ag layer on a side opposite to the glass layer, when a maximum value of intensity in a wavenumber range of 3,000 cm.sup.1 to 4,000 cm.sup.1 indicated by I.sub.A, and a maximum value of intensity in a wavenumber range of 450 cm.sup.1 to 550 cm.sup.1 is indicated by I.sub.B, I.sub.A/I.sub.B is 1.1 or greater.

A power module substrate with a Ag underlayer of the invention includes: a circuit layer that is formed on one surface of an insulating layer; and a Ag underlayer that is formed on the circuit layer, in which the Ag underlayer is composed of a glass layer that is formed on the circuit layer side and a Ag layer that is formed by lamination on the glass layer, and regarding the Ag underlayer, in a Raman spectrum obtained by a Raman spectroscopy with incident light made incident from a surface of the Ag layer on a side opposite to the glass layer, when a maximum value of intensity in a wavenumber range of 3,000 cm.sup.1 to 4,000 cm.sup.1 indicated by I.sub.A, and a maximum value of intensity in a wavenumber range of 450 cm.sup.1 to 550 cm.sup.1 is indicated by I.sub.B, I.sub.A/I.sub.B is 1.1 or greater.

A package structure and method of manufacturing is provided, whereby a bonding dielectric material layer is provided at a back side of a wafer, a bonding dielectric material layer is provided at a front side of an adjoining wafer, and wherein the bonding dielectric material layers are fusion bonded to each other.