An integrated circuit includes a first chip bonded to a second chip. The first chip includes gate all around transistors on a substrate. The first chip includes backside conductive vias extending through the substrate to the gate all around transistors. The second chip includes electronic circuitry electrically connected to the transistors by the backside conductive vias.

A multi-layer wafer and method of manufacturing such wafer are provided. The method comprises creating under bump metallization (UMB) pads on each of the two heterogeneous wafers; applying a conductive means above the UMB pads on at least one of the two heterogeneous wafers; and low temperature bonding the two heterogeneous wafers to adhere the UMB pads together via the conductive means. At least one stress compensating polymer layer may be applied to at least one of two heterogeneous wafers. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafer having UMB pads and at least one of the heterogeneous wafers having a stress compensating polymer layer and a conductive means applied above the UMB pads on at least one of the two heterogeneous wafers. The two heterogeneous wafers low temperature bonded together to adhere the UMB pads together via the conductive means.

A method for producing a structure by direct bonding of two elements, the method including: production of the elements to be assembled and assembly of the elements. The production of the elements to be assembled includes: deposition on a substrate of a TiN layer by physical vapor deposition, and deposition of a copper layer on the TiN layer. The assembly of the elements includes: polishing the surfaces of the copper layers intended to come into contact so that they have a roughness of less than 1 nm RMS and hydrophilic properties, bringing the surfaces into contact, and storing the structure at atmospheric pressure and at ambient temperature.

This method includes steps a) providing the first structure and second structure, the first structure including a surface on which a silicon layer is formed; b) bombarding the silicon layer by a beam (F) of species configured to reach the surface of the first structure, and to preserve a part of the silicon layer with a surface roughness of less than 1 nm RMS on completion of the bombardment; c) bonding the first structure and second structure by direct bonding between the part of the silicon layer preserved in step b) and the second structure, steps b) and c) being executed in the same chamber subjected to a vacuum of less than 10.sup.?2 mbar.

An integrated circuit die with two material layers having metal nano-particles and the method of forming the same are provided. The integrated circuit die includes a device layer comprising a first transistor, a first interconnect structure on a first side of the device layer, a first material layer on the first interconnect structure, wherein the first material layer comprises first metal nano-particles, and a second material layer bonded to the first material layer, wherein the second material layer comprises second metal nano-particles, and wherein the first material layer and the second material layer share an interface.

According to embodiments of the present disclosure, a semiconductor package is provided and may include: a substrate; a semiconductor chip on the substrate; a dummy chip on the semiconductor chip; and a first protection layer between the semiconductor chip and the dummy chip. The dummy chip may include: a semiconductor substrate including a first surface and a second surface, opposite to the first surface, the first surface being closer than the second surface to the semiconductor chip; a second protection layer on the first surface; and at least one penetration electrode penetrating the semiconductor substrate and the second protection layer. The at least one penetration electrode may be spaced apart from the semiconductor chip in a first direction perpendicular to a top surface of the semiconductor chip, and the first protection layer may be in contact with the second protection layer.

A semiconductor device comprising a first semiconductor component and a composite bonding layer on the first semiconductor component. The composite bonding layer comprises a dielectric stress buffer layer and a dielectric planarization layer, wherein a hardness of the dielectric stress buffer layer is greater than a hardness of the dielectric planarization layer. The semiconductor device further includes a second semiconductor component bonded to the first semiconductor component by insulator-to-insulator bonding between the composite bonding layer and an insulating bonding layer on the second semiconductor component, wherein the dielectric planarization layer is disposed an interface between the composite bonding layer and the insulating bonding layer.

This method includes steps a) providing the first structure and second structure, the first structure including a surface on which a silicon layer is formed; b) bombarding the silicon layer by a beam (F) of species configured to reach the surface of the first structure, and to preserve a part of the silicon layer with a surface roughness of less than 1 nm RMS on completion of the bombardment; c) bonding the first structure and second structure by direct bonding between the part of the silicon layer preserved in step b) and the second structure, steps b) and c) being executed in the same chamber subjected to a vacuum of less than 10.sup.2 mbar.

A method for bonding of a first, at least partially metallic contact surface of a first substrate to a second, at least partially metallic contact surface of a second substrate, with the following steps, especially the following progression: application of a sacrificial layer which is at least partially, especially predominantly soluble in the material of at least one of the contact surfaces to at least one of the contact surfaces, bonding of the contact surfaces with at least partial solution of the sacrificial layer in at least one of the contact surfaces.

A method for bonding of a first, at least partially metallic contact surface of a first substrate to a second, at least partially metallic contact surface of a second substrate, with the following steps, especially the following progression: application of a sacrificial layer which is at least partially, especially predominantly soluble in the material of at least one of the contact surfaces to at least one of the contact surfaces, bonding of the contact surfaces with at least partial solution of the sacrificial layer in at least one of the contact surfaces.