A semiconductor device includes a first electronic component, a second electronic component and a plurality of interconnection structures. The first electronic component has a first surface. The second electronic component is over the first electronic component, and the second electronic component has a second surface facing the first surface of the first electronic component. The interconnection structures are between and electrically connected to the first electronic component and the second electronic component, wherein each of the interconnection structures has a length along a first direction substantially parallel to the first surface and the second surface, a width along a second direction substantially parallel to the first surface and the second surface and substantially perpendicular to the first direction, and the length is larger than the width of at least one of the interconnection structures.

A manufacturing method of a semiconductor apparatus in which a semiconductor chip is joined to a target object, the manufacturing method including forming, in a joining region between the semiconductor chip and the target object where the semiconductor chip and the target object should be joined to each other, a plurality of metal paste patterns with a gap being provided in at least a part along a thickness direction between one another, and joining the semiconductor chip and the target object by sintering the plurality of metal paste patterns sandwiched between the semiconductor chip and the target object in a state where the gap exists between one another.

A semiconductor device includes: an insulating substrate; an aluminum pattern made of a pure aluminum or alloy aluminum material and formed on the insulating substrate; a plating formed on a surface of the aluminum pattern; and a semiconductor element joined to the plating, wherein a thickness of the plating is 10 m or more.

A semiconductor package structure is provided. The semiconductor package structure includes a chip structure. The semiconductor package structure includes a first conductive structure over the chip structure. The first conductive structure is electrically connected to the chip structure. The first conductive structure includes a first transition layer over the chip structure, and a first conductive layer on the first transition layer. The first conductive layer is substantially made of twinned copper.

A semiconductor device includes: a metal sheet; an insulating pattern provided on the metal sheet; a power circuit pattern and a signal circuit pattern that are provided on the insulating pattern; a power semiconductor chip mounted on the power circuit pattern; and a control semiconductor chip that is mounted on the signal circuit pattern and controls the power semiconductor chip. The power semiconductor chip is bonded to the power circuit pattern with a first die bonding material comprised of copper, and the control semiconductor chip is bonded to the signal circuit pattern with a second die bonding material.

A semiconductor die stack includes a base die and core dies stacked over the base die. Each of the base die and the core dies include a semiconductor substrate, a front side passivation layer formed over a front side of the semiconductor substrate, a back side passivation layer over a back side of the semiconductor substrate, a through-via vertically penetrating the semiconductor substrate and the front side passivation layer, and a bump, a support pattern, and a bonding insulating layer formed over the front side passivation layer. Top surfaces of the bump, the support pattern, and the bonding insulating layer are co-planar. The bump is vertically aligned with the through-via. The support pattern is spaced apart from the through-via and the bump. The support pattern includes a plurality of first bars that extend in parallel with each other in a first direction and a plurality of second bars that extend in parallel with each other in a second direction.

An electronic device, including: a conductive element having a conductive region on a front surface thereof; a fixing element having a fixing region on a front surface thereof, the fixing element being located apart from the conductive element in a plan view of the electronic device; and a wiring member having a flat plate shape. The wiring member includes a first portion bonded to the conductive region of the conductive element, a second portion fixed to the fixing region of the fixing element, and an inclined portion between the first portion and the second portion, the inclined portion being elastically deformable. In a side view of the electronic device, the conductive region of the conductive element and the fixing region of the fixing element are at different heights in a thickness direction of the electronic device.

An electronic power device including: a first electronic power component in which all the electrodes are arranged at a first main face of the first electronic power component; and an electric contact element in which a first main face is arranged against the first main face of the first electronic power component and which includes plural separate electrically conductive portions to which the electrodes of the first electronic power component are electrically connected. The first electronic power component and the electric contact element together form a stack such that a first lateral face of each of the portions of the electric contact element, substantially perpendicular to the first main face of the electric contact element, is arranged against at least one metallization of a support forming an electric contact of the first electronic power component.

A semiconductor device includes a first insulating material, a first conductor pattern provided on an upper surface of the first insulating material, a second conductor pattern provided on a lower surface of the first insulating material, a semiconductor element bonded to an upper surface of the first conductor pattern by a first bonding material, and a first base plate bonded to a lower surface of the second conductor pattern by a second bonding material, in which a ratio .sub.1/D.sub.1 satisfies .sub.1/D.sub.13510.sup.4W/(m.sup.2K) where .sub.1 represents thermal conductivity of the first insulating material and D.sub.1 represents a thickness of the first insulating material, solidus temperature of the first bonding material is equal to or higher than solidus temperature of the second bonding material, and a difference between the solidus temperature of the first bonding material and the solidus temperature of the second bonding material is within 40 C.

A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor structure. The semiconductor structure has a central portion and a peripheral portion surrounding the central portion. The method includes forming first conductive bumps and dummy conductive bumps over a surface of the semiconductor structure. The first conductive bumps are over the central portion and electrically connected to the semiconductor structure. The dummy conductive bumps are over the peripheral portion and electrically insulated from the semiconductor structure. The first conductive bumps each have a first thickness and a first width. The dummy conductive bumps each have a second thickness and a second width. The second thickness is less than the first thickness. The second width is greater than the first width.