An adhesive film includes a porous metal layer having a plurality of pores therein, a first adhesive layer on one side of the porous metal layer, an adhesive substance at least partially filling the pores of the porous metal layer, and a plurality of first thermal conductive members distributed in the first adhesive layer.

Representative implementations of techniques and methods include chemical mechanical polishing for hybrid bonding. The disclosed methods include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. Additionally, the conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.

There is provided an imaging device, an electronic apparatus including an imaging device, and an automotive vehicle including an electronic apparatus including an imaging device, including: a first substrate including a first set of photoelectric conversion units; a second substrate including a second set of photoelectric conversion units; and an insulating layer between the first substrate and the second substrate; where the insulating layer has a capability to reflect a first wavelength range of light and transmit a second wavelength range of light that is longer than the first wavelength range of light.

Various embodiments include a circuit carrier comprising: an installation place for an electronic component; and a deposit of a joining adjuvant applied to the installation place. The installation place has at an edge, a recess forming a depression in a surface of the circuit carrier. The deposit comprises a sintered material with a protuberance at an edge of the deposit.

A semiconductor die stack includes a base die and core dies stacked over the base die. Each of the base die and the core dies include a semiconductor substrate, a front side passivation layer formed over a front side of the semiconductor substrate, a back side passivation layer over a back side of the semiconductor substrate, a through-via vertically penetrating the semiconductor substrate and the front side passivation layer, and a bump, a support pattern, and a bonding insulating layer formed over the front side passivation layer. Top surfaces of the bump, the support pattern, and the bonding insulating layer are co-planar. The bump is vertically aligned with the through-via. The support pattern is spaced apart from the through-via and the bump. The support pattern includes a plurality of first bars that extend in parallel with each other in a first direction and a plurality of second bars that extend in parallel with each other in a second direction.

Implementations of a semiconductor package may include a pin coupled to a substrate. The pin may include a titanium sublayer, a nickel sublayer, and one of a silver and tin intermetallic layer or a copper and tin intermetallic layer, the one of the silver and tin intermetallic layer or the copper and tin intermetallic layer having a melting temperature greater than 260 degrees Celsius. The one of the silver and tin intermetallic layer or the copper and tin intermetallic layer may be formed by reflowing a tin layer and one of a silver layer or copper layer with a silver layer of the substrate where the substrate may be directly coupled to the one of the silver and tin intermetallic layer or the copper and tin intermetallic layer. The substrate may include a copper layer that was directly coupled with the silver layer before the reflow.

The semiconductor device includes first and second semiconductor elements. Each element has an obverse surface and a reverse surface, with a first electrode arranged on the reverse surface, and with a second electrode arranged on the obverse surface. The semiconductor device further includes: a first lead having an obverse surface and a reverse surface; an insulating layer covering the first lead, the first semiconductor element and the second semiconductor element; a first electrode connected to the second electrode of the first semiconductor element; and a second electrode connected to the first lead. The first semiconductor element and the first lead are bonded to each other with the reverse surface of the first semiconductor element facing the lead obverse surface. The second semiconductor element and the first lead are bonded to each other with the reverse surface of the second semiconductor element facing the lead reverse surface.

Provided is a display assembly including a plurality of light emitting diodes, a plurality of electrodes provided on the plurality of light emitting diodes, a substrate, a plurality of electrode pads provided on the substrate, the plurality of electrode pads being connected to the electrodes provided on the plurality of light emitting diodes, and an adhesive layer fixing the plurality of light emitting diodes to the substrate, wherein the adhesive layer includes a non-conductive polymer resin, a flux agent mixed with the non-conductive polymer resin, and a plurality of conductive particles dispersed in the non-conductive polymer resin and connecting the electrodes of the light emitting diodes and the plurality of electrode pads.

An adhesive film includes a porous metal layer having a plurality of pores therein, a first adhesive layer on one side of the porous metal layer, an adhesive substance at least partially filling the pores of the porous metal layer, and a plurality of first thermal conductive members distributed in the first adhesive layer.

A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate and forming a first adhesive element directly on the chip structure. The first adhesive element has a first thermal conductivity. The method also includes forming a second adhesive element directly on the chip structure. The second adhesive element has a second thermal conductivity, and the second thermal conductivity is greater than the first thermal conductivity. The method further includes attaching a protective lid to the chip structure through the first adhesive element and the second adhesive element.