The disclosed embodiments of electronic packages include electrical contact pad features present on all sides of the package that facilitate simple and low cost electrical connections to the package made through a mechanical contacting scheme. In an embodiment, an electronic package comprises: a metal leadframe having a first leadframe portion having a first thickness and a second leadframe portion having a second thickness that is less than the first thickness, the second leadframe portion defining electrical contact pads; a silicon die attached to the second leadframe portion and overlying a space formed in the leadframe by the first and second leadframe portions; and wirebonds coupling the silicon die to the electrical contact pads. A method of fabricating the electronic package is also disclosed.

An electronic device includes: a first semiconductor die having a metal region; a substrate having a plurality of metal regions; a first soldered joint between the metal region of the first semiconductor die and a first metal region of the substrate, the first soldered joint having one or more intermetallic phases throughout the entire soldered joint, each of the one or more intermetallic phases formed from a solder preform diffused into the metal region of the first semiconductor die and the first metal region of the substrate; and a second semiconductor die soldered to the first or different metal region of the substrate.

An electronic device includes: a first semiconductor die having a metal region; a substrate having a plurality of metal regions; a first soldered joint between the metal region of the first semiconductor die and a first metal region of the substrate, the first soldered joint having one or more intermetallic phases throughout the entire soldered joint, each of the one or more intermetallic phases formed from a solder preform diffused into the metal region of the first semiconductor die and the first metal region of the substrate; and a second semiconductor die soldered to the first or different metal region of the substrate.

Disclosed are an array substrate, and a display device, and a method for manufacturing the same. The array substrate includes: a base substrate, and a thin film transistor, a planarization pattern, a bonding pattern, and a conductive structure that are disposed on the base substrate. The thin film transistor, the planarization pattern, and the bonding pattern are laminated in a direction going distally from the base substrate. The planarization pattern is provided with a via and a groove, the conductive structure is disposed in the via, wherein the bonding pattern is conductive and is electrically connected to the thin film transistor by the conductive structure, an orthographic projection of the bonding pattern on the base substrate falls outside an orthographic projection of the groove on the base substrate, and the groove is configured to accommodate an adhesive.

Disclosed are an array substrate, and a display device, and a method for manufacturing the same. The array substrate includes: a base substrate, and a thin film transistor, a planarization pattern, a bonding pattern, and a conductive structure that are disposed on the base substrate. The thin film transistor, the planarization pattern, and the bonding pattern are laminated in a direction going distally from the base substrate. The planarization pattern is provided with a via and a groove, the conductive structure is disposed in the via, wherein the bonding pattern is conductive and is electrically connected to the thin film transistor by the conductive structure, an orthographic projection of the bonding pattern on the base substrate falls outside an orthographic projection of the groove on the base substrate, and the groove is configured to accommodate an adhesive.

An electronic device includes a substrate, a first pad disposed on the substrate, a second pad disposed opposite to the first pad, and a conductive particle disposed between the first pad and the second pad. The first pad has a recess, and a part of the conductive particle sinks in the recess.

An electronic device includes a substrate, a first pad disposed on the substrate, a second pad disposed opposite to the first pad, and a conductive particle disposed between the first pad and the second pad. The first pad has a recess, and a part of the conductive particle sinks in the recess.

A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill.

An electronic device includes a substrate, a first pad disposed on the substrate and having a first conductive layer and a second conductive layer disposed on the first conductive layer, a first insulating layer disposed on the first conductive layer and having at least one opening exposing a portion of the first conductive layer, and a second pad disposed opposite to the first pad. The second conductive layer is disposed on the first conductive layer in the at least one opening and extends over the at least one opening to be disposed on a portion of the insulating layer. A bottom of the least one opening of the first insulating layer has an arc edge in a top view of the electronic device.

An electronic device includes a substrate, a first pad disposed on the substrate and having a first conductive layer and a second conductive layer disposed on the first conductive layer, a first insulating layer disposed on the first conductive layer and having at least one opening exposing a portion of the first conductive layer, and a second pad disposed opposite to the first pad. The second conductive layer is disposed on the first conductive layer in the at least one opening and extends over the at least one opening to be disposed on a portion of the insulating layer. A bottom of the least one opening of the first insulating layer has an arc edge in a top view of the electronic device.