Provided is a package structure including a photonic die, an electronic die, a conductive layer, a circuit substrate, and an underfill. The electronic die is bonded on a front side of the photonic die. The conductive layer is disposed on a back side of the photonic die. The conductive layer includes a plurality of conductive pads and a dam structure between the conductive pads and a first sidewall of the photonic die. The circuit substrate is bonded on the back side of the photonic die through a plurality of connectors and the conductive pads. The underfill laterally encapsulates the connectors, the conductive pads, and the dam structure. The underfill at the first sidewall of the photonic die has a first height, the underfill at a second sidewall of the photonic die has a second height, and the first height is lower than the second height.

A 3DIC structure includes a die, a conductive terminal, and a dielectric structure. The die is bonded to a carrier through a bonding film. The conductive terminal is disposed over and electrically connected to the die. The dielectric structure comprises a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed laterally aside the die. The second dielectric layer is disposed between the first dielectric layer and the bonding film, and between the die and the boding film. A second edge of the second dielectric layer is more flat than a first edge of the first dielectric layer.

A flexible foil-based package is disclosed which comprises at least one flexible foil substrate on which at least one electronic device is mounted in flip-chip mounting technology. The flexible foil substrate is bent so that a recess is created in which the electronic device is arranged. A casting compound is applied to cover the electronic device.

Disclosed is a semiconductor package comprising a lower substrate including a conductive line; a first semiconductor chip on the lower substrate; an under-fill layer between the first semiconductor chip and the lower substrate, the under-fill layer including a central part below the first semiconductor chip and an edge part isolated from direct contact with the central part in a first direction parallel to a top surface of the lower substrate, and a recess region between the central part and the edge part. The recess region may be defined by a sidewall of the central part, a sidewall of the edge part, and a top surface of the conductive line in the lower substrate.

A fan-out packaging method employing a combined process includes: manufacturing at least two layers of basic circuit patterns on a substrate; manufacturing a galvanic isolation layer on one of the two layers of basic circuit patterns; manufacturing a fine circuit pattern on the galvanic isolation layer; using a bonding layer to bond an electronic component to the galvanic isolation layer, and using a patch material to establish an electrical connection between the electronic component and the fine circuit pattern; and using a packaging layer to package the electronic component, wherein the fine circuit pattern has a width less than widths of the basic circuit patterns. In the present disclosure, multiple layers of circuits are manufactured before installation and packaging of electronic components, thereby reducing the number of times an insulation material is to be heated, and broadening the range of available types of insulation materials.

A method of soldering includes providing a substrate having a first metal joining surface, providing a semiconductor die having a second metal joining surface, providing a solder preform having a first interface surface and a second interface surface, arranging the solder preform between the substrate and the semiconductor die such that the first interface surface faces the first metal joining surface and such that the second interface surface faces the second metal joining surface, and performing a mechanical pressure-free diffusion soldering process that forms a soldered joint between the substrate and the semiconductor die by melting the solder preform and forming intermetallic phases in the solder. One or both of the first interface surface and the second interface surface has a varying surface profile that creates voids between the solder preform and one or both of the substrate and the semiconductor die before the melting of the solder preform.

A method of soldering includes providing a substrate having a first metal joining surface, providing a semiconductor die having a second metal joining surface, providing a solder preform having a first interface surface and a second interface surface, arranging the solder preform between the substrate and the semiconductor die such that the first interface surface faces the first metal joining surface and such that the second interface surface faces the second metal joining surface, and performing a mechanical pressure-free diffusion soldering process that forms a soldered joint between the substrate and the semiconductor die by melting the solder preform and forming intermetallic phases in the solder. One or both of the first interface surface and the second interface surface has a varying surface profile that creates voids between the solder preform and one or both of the substrate and the semiconductor die before the melting of the solder preform.

A display device includes a first electrode disposed on a substrate, a second electrode disposed on the substrate and spaced apart from the first electrode, at least one light-emitting element extending in a direction, disposed between the first electrode and the second electrode, and electrically connected to the first electrode and the second electrode, and an insulating pattern layer disposed on the first electrode and the second electrode, the insulating pattern layer including a fixer disposed on at least part of the at least one light-emitting element, and a barrier surrounding the at least one light-emitting element.

A semiconductor structure and methods for forming the same including a package comprising at least one semiconductor die, a redistribution structure comprising bonding pads, and a first underfill material portion located between the at least one semiconductor die and the redistribution structure, a substrate package comprising chip-side bonding pads and at least one substrate trench, in which the at least one substrate trench extends vertically below a top surface of the substrate package in a cross-section view, solder material portions bonded to the chip-side bonding pads and the bonding pads, and a second underfill material portion laterally surrounding the solder material portions and dispensed within the at least one substrate trench.

A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities.