A semiconductor device includes a first electronic component, a second electronic component, a third electronic component, a plurality of first interconnection structures, and a plurality of second interconnection structures. The second electronic component is between the first electronic component and the third electronic component. The first interconnection structures are between and electrically connected to the first electronic component and the second electronic component. Each of the first interconnection structures has a length along a first direction substantially parallel to a surface of the first electronic component and a width along a second direction substantially parallel to the surface and substantially perpendicular to the first direction. The length is larger than the width. The second interconnection structures are between and electrically connected to the second electronic component and the third electronic component.

According to one embodiment, a semiconductor device includes a semiconductor chip, and a die pad. The die pad has a first surface. The semiconductor chip is bonded on the first surface using a paste including a metal particle. A concave structure is provided in the first surface. The concave structure is positioned directly under each of a plurality of sides of the semiconductor chip and extends along each of the plurality of sides.

A semiconductor device includes a first electronic component, a second electronic component and a plurality of interconnection structures. The first electronic component has a first surface. The second electronic component is over the first electronic component, and the second electronic component has a second surface facing the first surface of the first electronic component. The interconnection structures are between and electrically connected to the first electronic component and the second electronic component, wherein each of the interconnection structures has a length along a first direction substantially parallel to the first surface and the second surface, a width along a second direction substantially parallel to the first surface and the second surface and substantially perpendicular to the first direction, and the length is larger than the width of at least one of the interconnection structures.

A semiconductor device includes a first electronic component, a second electronic component and a plurality of interconnection structures. The first electronic component has a first surface. The second electronic component is over the first electronic component, and the second electronic component has a second surface facing the first surface of the first electronic component. The interconnection structures are between and electrically connected to the first electronic component and the second electronic component, wherein each of the interconnection structures has a length along a first direction substantially parallel to the first surface and the second surface, a width along a second direction substantially parallel to the first surface and the second surface and substantially perpendicular to the first direction, and the length is larger than the width of at least one of the interconnection structures.

A measuring device includes two sensor chips that measure a flow rate of a fluid flowing through a pipe, electrode pads extending from a temperature measuring section and from a heater, respectively, toward peripheries of the two sensor chips, and wires that are electrically connected to the electrode pads and via which a measurement signal that is output from the temperature measuring section or the heater is transmitted to outside of the sensor chips. Each of the electrode pads includes a straight portion that extends linearly from the temperature measuring section or the heater and a wide portion that is formed at a leading end of each of the electrode pads and is wider than the straight portion, and an entire surface area of the wide portion is set as a wire-bonding-allowed region, to which one of the wires is to be bonded.

An anisotropic conductive film that is capable of suppressing the occurrence of short circuit during anisotropic conductive connection of electrical components having decreased pitch, and suppressing a decrease in conduction reliability during storage under a high temperature and high humidity environment has a structure in which a conductive particle-containing layer containing conductive particles that are arranged in a single layer in a layered binder resin composition is layered on at least a first insulating resin composition layer. The lowest melt viscosity of the binder resin composition is equal to or higher than that of a first insulating resin composition. A second insulating resin composition layer is further layered on a surface of the conductive particle-containing layer on a side opposite to the first insulating resin composition layer. The lowest melt viscosity of the binder resin composition is higher than those of the first and second insulating resin compositions.

An anisotropic conductive film that is capable of suppressing the occurrence of short circuit during anisotropic conductive connection of electrical components having decreased pitch, and suppressing a decrease in conduction reliability during storage under a high temperature and high humidity environment has a structure in which a conductive particle-containing layer containing conductive particles that are arranged in a single layer in a layered binder resin composition is layered on at least a first insulating resin composition layer. The lowest melt viscosity of the binder resin composition is equal to or higher than that of a first insulating resin composition. A second insulating resin composition layer is further layered on a surface of the conductive particle-containing layer on a side opposite to the first insulating resin composition layer. The lowest melt viscosity of the binder resin composition is higher than those of the first and second insulating resin compositions.

A capacitor component includes a support member; capacitance laminates laminated on one surface of the support member; at least one insulating layer disposed between the capacitance laminates; and a plurality of through structures each penetrating through at least one of the capacitance laminates. Each of the capacitance laminates includes a first electrode layer, a second electrode layer, and a dielectric layer disposed between the first and second electrode layers. One of the plurality of through structures includes a connection conductive pillar connected between first electrode layers of the capacitance laminates. Another of the plurality of through structures includes a first conductive pillar connected to a first electrode layer of one of the capacitance laminates, a dielectric through portion surrounding the first conductive pillar; and a through connection portion surrounding the dielectric through portion and connecting second electrode layers of the capacitance laminates to each other.

Electronic assembly methods and structures are described. In an embodiment, an electronic assembly method includes bringing together an electronic component and a routing substrate, and directing a large area photonic soldering light pulse toward the electronic component to bond the electronic component to the routing substrate.

A measuring device includes two sensor chips that measure a flow rate of a fluid flowing through a pipe, electrode pads extending from a temperature measuring section and from a heater, respectively, toward peripheries of the two sensor chips, and wires that are electrically connected to the electrode pads and via which a measurement signal that is output from the temperature measuring section or the heater is transmitted to outside of the sensor chips. Each of the electrode pads includes a straight portion that extends linearly from the temperature measuring section or the heater and a wide portion that is formed at a leading end of each of the electrode pads and is wider than the straight portion, and an entire surface area of the wide portion is set as a wire-bonding-allowed region, to which one of the wires is to be bonded.