In an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.

Provided is a solder alloy including an Sb content of 3 wt % or more and 15 wt % or less, a Te content of 0.01 wt % or more and 1.5 wt % or less, an Au content of 0.005 wt % or more and 1 wt % or less, and a remainder that is Sn.

A power-module substrate unit having at least one power-module substrate including one ceramic substrate, a circuit layer formed on one surface of the ceramic substrate, and a metal layer formed on another surface of the ceramic substrate, and a heat sink on which the metal layer of the power-module substrate is bonded, in which the metal layer is made of an aluminum plate having purity of 99.99 mass % or higher; the heat sink is made of an aluminum plate having purity of 99.90 mass % or lower; and the circuit layer has a stacking structure of a first layer made of an aluminum plate having the purity of 99.99 mass % or higher and being bonded to the ceramic substrate and a second layer made of the aluminum plate having the purity lower than 99.90 mass % and being bonded on a surface of the first layer.

A semiconductor chip includes a single-crystal substrate and a metal electrode on the bottom surface of the substrate. The metal electrode has a region in which a first metal is exposed and a region in which a second metal is exposed, the second metal having a standard electrode potential different from that of the first metal.

Bonded surfaces are formed by adhering first nanorods and second nanorods to respective first and second surfaces. The first shell is formed on the first nanorods and the second shell is formed on the second nanorods, wherein at least one of the first nanorods and second nanorods, and the first shell and the second shell are formed of distinct metals. The surfaces are then exposed to at least one condition that causes the distinct metals to form an alloy, such as eutectic alloy having a melting point below the temperature at which the alloy is formed, thereby bonding the surfaces upon which solidification of the alloy.

Various embodiments disclosed relate to an integrated circuit package. The integrated circuit package includes a substrate. A first die is attached to the substrate. The integrated circuit package further includes a second die. A thermally conductive layer is disposed between the first die and the second die. A first thermal conductivity of the layer in a first direction is greater than a second thermal conductivity of the layer in a second direction.

A semiconductor device includes: a first element formed of a first constituent as a main constituent; a second element formed of a second constituent as a main constituent; a heat sink on which the first element and the second element are disposed; a first connection layer electrically connecting the first element to the heat sink; a second connection layer electrically connecting the second element to the heat sink; and a mold resin covering and protecting the first element, the second element and the heat sink. Sizes of the first element and the second element are set so that an equivalent plastic strain increment of the first connection layer is greater than the second connection layer. Accordingly, in the semiconductor device including semiconductor elements formed of different constituents, the elements are thermally protected without providing a temperature detector to the semiconductor element formed of one of the constituents.

A semiconductor chip includes a substrate, an electrode pad formed on the substrate, an insulating layer covering the substrate and the electrode pad, and having an opening exposing a portion of a surface of the electrode pad, a first conductive layer formed on the exposed portion of the surface of the electrode pad and extending to a surface of the insulating layer, and a second conductive layer formed on the first conductive layer, covering the first conductive layer in a plan view, and having an outer edge portion which is located further out than an outer edge of the first conductive layer in a plan view. The outer edge portion of the second conductive layer has at least one curved portion. At least one portion of the curved portion is located between the outer edge of the first conductive layer and an outer edge of the second conductive layer in a plan view.

A flip-chip mounting structure includes a first member including a first electrode pad, a bump formed on the first electrode pad, a second member including a second electrode pad, and a connection portion formed on the second electrode pad. The first member and the second member are flip-chip mounted, and the first electrode pad and the second electrode pad are electrically connected via the bump and the bonding portion. The bonding portion includes at least a first bonding portion formed in a region sandwiched between a top portion of the bump and the second electrode pad, and a second bonding portion formed in a region surrounding a periphery of the first bonding portion and a region surrounding at least a side surface of the bump. Each of the first bonding portion and the second bonding portion is made of a sintered body of a metal powder.

A bonding member (10) includes surface-processed silver surfaces (11a, 11b).