A bonding member (10) includes surface-processed silver surfaces (11a, 11b).

Provided is a technique of improving joint strength between a joining layer and a resin. A power semiconductor device includes a wiring member, a semiconductor element, a joining layer joining the wiring member and the semiconductor element to each other, and a resin covering the wiring member, the semiconductor element, and the joining layer. The joining layer includes a first joining layer provided to be adjacent to the resin and having a void filled with the resin. A filler contained in the resin has a maximum width greater than a minimum diameter of the void in the first joining layer.

A method for cohesively connecting a first component of a power semiconductor module to a second component of a power semiconductor module by sintering, the method comprising the steps of: applying a layer of unsintered sinter material to a predetermined bonding surface of the first component, arranging the second component on the surface layer of unsintered sinter material, attaching the second component to the first component by applying pressure and/or temperature on a locally delimited partial area within the predetermined bonding surface, processing the first and/or second component and/or other components of the power semiconductor module, and complete-area sintering of the sinter material.

A cooling bond layer for a power electronics assembly is provided. The cooling bond layer includes a first end, a second end spaced apart from the first end, a metal matrix extending between the first end and the second end, and a plurality of micro-channels extending through the metal matrix from the first end to the second end. The plurality of micro-channels are configured for a cooling fluid to flow through and remove heat from the cooling bond layer. In some embodiments, the plurality of micro-channels are cylindrical shaped micro-channels. In such embodiments, the plurality of micro-channels may have a generally constant average inner diameter along a thickness of the cooling bond layer. In the alternative, the plurality of micro-channels may have a graded average inner diameter along a thickness of the cooling bond layer. In other embodiments, the plurality of micro-channels may have a wire mesh layered structure.

A cooling bond layer for a power electronics assembly is provided. The cooling bond layer includes a first end, a second end spaced apart from the first end, a metal matrix extending between the first end and the second end, and a plurality of micro-channels extending through the metal matrix from the first end to the second end. The plurality of micro-channels are configured for a cooling fluid to flow through and remove heat from the cooling bond layer. In some embodiments, the plurality of micro-channels are cylindrical shaped micro-channels. In such embodiments, the plurality of micro-channels may have a generally constant average inner diameter along a thickness of the cooling bond layer. In the alternative, the plurality of micro-channels may have a graded average inner diameter along a thickness of the cooling bond layer. In other embodiments, the plurality of micro-channels may have a wire mesh layered structure.

A microelectronic assembly includes a first substrate having a surface and a first conductive element and a second substrate having a surface and a second conductive element. The assembly further includes an electrically conductive alloy mass joined to the first and second conductive elements. First and second materials of the alloy mass each have a melting point lower than a melting point of the alloy. A concentration of the first material varies in concentration from a relatively higher amount at a location disposed toward the first conductive element to a relatively lower amount toward the second conductive element, and a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the second conductive element to a relatively lower amount toward the first conductive element.

A microelectronic assembly includes a first substrate having a surface and a first conductive element and a second substrate having a surface and a second conductive element. The assembly further includes an electrically conductive alloy mass joined to the first and second conductive elements. First and second materials of the alloy mass each have a melting point lower than a melting point of the alloy. A concentration of the first material varies in concentration from a relatively higher amount at a location disposed toward the first conductive element to a relatively lower amount toward the second conductive element, and a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the second conductive element to a relatively lower amount toward the first conductive element.

Provided is a technique of improving joint strength between a joining layer and a resin. A power semiconductor device includes a wiring member, a semiconductor element, a joining layer joining the wiring member and the semiconductor element to each other, and a resin covering the wiring member, the semiconductor element, and the joining layer. The joining layer includes a first joining layer provided to be adjacent to the resin and having a void filled with the resin. A filler contained in the resin has a maximum width greater than a minimum diameter of the void in the first joining layer.

A semiconductor device includes a conductive member, a solder layer, a chip, a coating film, an insulating part, and a sealing resin. The solder layer is located on the conductive member. The chip is located on the solder layer. The coating film is insulative. The coating film is located on the chip. The coating film includes a first covering part. The first covering part covers an outer perimeter edge of an upper surface of the chip. The insulating part is located on the coating film. The sealing resin seals the solder layer, the chip, the coating film, and the insulating part.

According to one embodiment, a semiconductor device includes a first semiconductor element having a first surface, a second semiconductor element having a lower surface bonded to the first surface of the first semiconductor element, a gel-like silicone that covers an upper surface of the second semiconductor element, and a resin portion that covers the gel-like silicone and the first surface of the first semiconductor element.