A stack package includes a second semiconductor die stacked on the first semiconductor die, a third semiconductor die disposed on the lifting supporter. The third semiconductor die vertically and partially overlapping with the second semiconductor die.

An electronic apparatus includes an electronic panel including a first pad part and a second pad part having a portion electrically connected to the first pad part, a driving circuit including a bump part overlapping the first pad part in a plan view, and a circuit board including a lead part overlapping the second pad part in a plan view. The lead part including a plurality of test leads includes a first test lead group electrically connected to the first pad part, and a second test lead group insulated from the first pad part, and one test lead of the first test lead group and one test lead of the second test lead group are electrically connected to each other.

This disclosure is related to arranging micro devices in the donor substrate by either patterning or population so that there is no interfering with unwanted pads and the non-interfering area in the donor substrate is maximized. This enables to transfer the devices to receiver substrate with fewer steps.

A semiconductor device according to the present invention includes a relay substrate provided on a plurality of semiconductor chips. The relay substrate includes an insulating plate in which a through hole is formed, a lower conductor provided on a lower surface of the insulating plate and having a first lower conductor and a second lower conductor, an upper conductor provided on an upper surface of the insulating plate, a connection part provided in the through hole and connecting the second lower conductor and the upper conductor together, and a protruding part which is a part of one of the first lower conductor and the upper conductor and protrudes outward from the insulating plate, the protruding part is connected to a first external electrode, and another of the first lower conductor and the upper conductor is connected to a second external electrode and is positioned inside the insulating plate.

Provided are a semiconductor device which is provided with a circuit board and capable of suppressing an increase in its footprint, and a power conversion apparatus including the semiconductor device. The semiconductor device includes a circuit board, a power semiconductor element, an insulating block, a control signal terminal, a first main terminal, and a second main terminal. The insulating block is disposed so as to surround the power semiconductor element. The control signal terminal is inserted into the insulating block and thereby fixed to the insulating block. The control signal terminal includes a bent portion which partially protrudes above the power semiconductor element from the insulating block, and is bonded to the power semiconductor element. The first main terminal is bonded to the same power semiconductor element as the power semiconductor element to which the control signal terminal is bonded. The second main terminal is bonded to the circuit board.

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

A light-emitting device includes a first light-emitting element, a second light-emitting element having a peak emission wavelength different from that of the first light-emitting element, a light-guide member covering a light extracting surface and lateral surfaces of the first light-emitting element and a light extracting surface and lateral surfaces of the second light-emitting element, and a wavelength conversion layer continuously covering the light extracting surface of each of the first and second light-emitting elements and disposed apart from each of the first and second light-emitting elements, and a first reflective member covering outer lateral surfaces of the light-guide member. An angle defined by an active layer of the first light-emitting element and an active layer of the second light-emitting element is less than 180 at a wavelength conversion layer side.

Provided is a power semiconductor device which is able to have improved connection reliability between a wiring line and an electrode of a power semiconductor element in comparison to conventional power semiconductor devices. This power semiconductor device is provided with: a semiconductor element; an insulating substrate having an electrode layer to which the semiconductor element is bonded; an external wiring line which is solder bonded to an upper surface electrode of the semiconductor element and has an end portion for external connection, said end portion being bent toward the upper surface; and a frame member which is affixed to the electrode layer of the insulating substrate. The frame member has a fitting portion that is fitted with the end portion for external connection; and the external wiring line has at least two projected portions that protrude toward the semiconductor element.

A semiconductor device that is capable of suitably dissipating heat from a semiconductor chip is proposed. The proposed semiconductor device may include a semiconductor chip provided with a semiconductor substrate and a surface electrode provided on a surface of the semiconductor substrate; and a conductive plate provided with a plate shape portion and a convex portion protruding from the plate shape portion. An end surface of the convex portion may be corrected to the surface electrode. A width of the end surface of the convex portion may be narrower than a width of a base portion of the convex portion on a plate shape portion side.

A method of manufacturing a semiconductor device that includes a resin package sealing a semiconductor element and a pair of metal plates interposing the semiconductor element therebetween, in which each of the pair of metal plates is exposed at corresponding one of both surfaces of the resin package is disclosed. The method may include preparing an assembly in which the semiconductor element is connected to the pair of metal plates; setting the assembly in a cavity of a mold, wherein one metal plate is in contact with a bottom surface of the cavity and a space is provided above the other metal plate; forming the resin package by injecting a molten resin into the cavity so as to cover an upper side of the other metal plate, stopping the injecting of the molten resin with a part of the space on an upper side of the cavity unfilled.