A die structure includes a first die having a first surface and a second surface opposite the first surface. The first die includes sidewalls extending between the first and second surfaces. The die structure includes conductive ink printed traces including a first group of the conductive ink printed traces on the first surface of the first semiconductor die. A second group of the conductive ink printed traces are on the second surface of the semiconductor die, and a third group of the conductive ink printed traces are on the sidewalls of the semiconductor die.

According to an embodiment, a semiconductor device includes a silicon substrate, a semiconductor layer, and a lower layer. The semiconductor layer is formed on an upper surface of the silicon substrate. The lower layer is formed on a lower surface of the silicon substrate and has a side surface connecting to a side surface of the silicon substrate. At least a pair of side surfaces of the semiconductor device has a curved shape widening from an upper side toward a lower side.

Apparatus(es) and method(s) relate generally to via arrays on a substrate. In one such apparatus, the substrate has a conductive layer. First plated conductors are in a first region extending from a surface of the conductive layer. Second plated conductors are in a second region extending from the surface of the conductive layer. The first plated conductors and the second plated conductors are external to the first substrate. The first region is disposed at least partially within the second region. The first plated conductors are of a first height. The second plated conductors are of a second height greater than the first height. A second substrate is coupled to first ends of the first plated conductors. The second substrate has at least one electronic component coupled thereto. A die is coupled to second ends of the second plated conductors. The die is located over the at least one electronic component.

A semiconductor package includes first semiconductor chips electrically connected to each other through a through-via electrically connecting a first front surface pad and a first rear surface pad. A second semiconductor chip has a second lower surface including a second front surface pad, a second upper surface, a second side surface extending from the second upper surface, and a recess surface extending from the second lower surface to the second side surface. First adhesive films are on a first lower surface of first semiconductor chips and include first extension portions extending further outwardly than a first side surface of the first semiconductor chips. A second adhesive film is on the second lower surface and includes a second extension portion extending further outwardly than the second side surface. In a horizontal direction, a length of the second extension portion is less than a length of each of the first extension portions.

A semiconductor package includes a substrate, a substrate pad on an upper surface of the substrate, first and second semiconductor chips stacked on the substrate in a first direction, wherein a sidewall of the first semiconductor chip and a sidewall of the second semiconductor chip are on the same plane, a first chip stack pad on an upper surface of the first semiconductor chip, a second chip stack pad on an upper surface of the second semiconductor chip, a first wire connecting the first chip stack pad with the substrate pad, and a second wire connecting the second chip stack pad with the substrate pad, wherein a first center of an upper surface of the first chip stack pad and a second center of an upper surface of the second chip stack pad are misaligned in the first direction.

In some embodiments, the present disclosure relates to an integrated chip including a substrate and a first die disposed over the substrate. A first plurality of die stopper bumps are disposed along a backside of the first die. The first plurality of die stopper bumps directly contact the backside of the first die, and the first plurality of die stopper bumps are arranged as a plurality of groups of die stopper bumps. A plurality of adhesive structures are also present. Each of the plurality of adhesive structures surrounds a corresponding group of the plurality of groups of die stopper bumps.

A semiconductor device includes: a base material having a first terminal; a semiconductor chip having a first electrode pad electrically connected with the first terminal, a second electrode pad to which a power supply potential is to be supplied, and a third electrode pad to which a reference potential is to be supplied, and mounted on the base material via a first member; a chip capacitor having a first electrode and a second electrode, and mounted on the semiconductor chip via a second member; a first wire electrically connecting the first electrode pad with the first terminal; a second wire electrically connecting the second electrode pad with the first electrode without going through the base material; and a third wire electrically connecting the third electrode pad with the second electrode without going through the base material.

A semiconductor package includes a first structure, a first semiconductor chip on the first structure, a first conductive pad on the first structure between the first structure and the first semiconductor chip, a second conductive pad on a lower surface of the first semiconductor chip and vertically overlapping the first conductive pad, a bump connecting the first conductive pad and the second conductive pad, a first adhesive layer surrounding at least a part of side walls of the bump and side walls of the first conductive pad, and a second adhesive layer surrounding at least a part of the side walls of the bump and side walls of the second conductive pad, the second adhesive layer including a material different from the first adhesive layer, wherein a horizontal width of the first adhesive layer is smaller than a horizontal width of the second adhesive layer.

A semiconductor package includes a first semiconductor chip including a support structure extending away from a top surface thereof, a second semiconductor chip stacked on the first semiconductor chip, having a horizontal width that is less than that of the first semiconductor chip, and having an edge horizontally spaced apart from that of the first semiconductor chip in a plan view, and an insulating adhesive layer between the first semiconductor chip and the second semiconductor chip that extends away from between the first semiconductor chip and the second semiconductor chip to cover the support structure. In a plan view, the support structure is horizontally spaced apart from the edge of the second semiconductor chip and an edge of the insulating adhesive layer.

A semiconductor device includes a metal member (15), a first semiconductor chip (13), a second semiconductor chip (14), a first solder (24) and a second solder (25). A quantity of heat generated in the first semiconductor chip is greater than the second semiconductor chip. The second semiconductor chip is formed of a material having larger Young's modulus than the first semiconductor chip. The first semiconductor chip has a first metal layer (13a) connected to the metal member through a first solder (24) at a surface facing the metal member. The second semiconductor chip has a second metal layer (14a) connected to the metal member through a second solder (25) at a surface facing the metal member. A thickness of the second solder is greater than a maximum thickness of the first solder at least at a portion of the second solder corresponding to a part of an outer peripheral edge of the second metal layer.