A semiconductor chip stack module that includes a substrate, two first semiconductor chips supported by the substrate, and a second semiconductor chip stacked on both of the two first semiconductor chips. The second semiconductor chip is electrically connected to both of the two first semiconductor chips by a conductive paste configured between the second semiconductor chip and both of the two first semiconductor chips. As multiple standard chips are stacked in the power module, and their number as well as the connection methods (e.g. series or parallel) are flexible so that the user can choose which electric characteristic(s) to be increased in the power module with the stacked chips.

A chip package including a semiconductor chip is provided. The chip package may include a packaging material at least partially around the semiconductor chip with an opening extending from a top surface of the packaging material to the semiconductor chip and/or to an electrical contact structure contacting the semiconductor chip, and a thermally conductive material in the opening, wherein the thermally conductive material is configured to transfer heat from the semiconductor chip to an outside, wherein the thermally conductive material extends laterally at least partially over the top surface of the packaging material.

The present disclosure relates to techniques for manufacturing a semiconductor package assembly, with a semiconductor die structure mounted to a lead frame having terminals and encapsulated with a molding resin, as well as a semiconductor package assembly obtained with these techniques. An object of the present disclosure is to provide a manufacturing technique that results in a leaded/leadless power/MCD package or power module manufactured with less complex and less time-consuming process steps, and the connecting elements being implemented are of a straightforward design with reduced R.sub.DS(on) characteristic.

In an embodiment a carrier includes a shaped body, a lead frame, a first electrode and a second electrode, wherein the first electrode includes a first subregion of the lead frame, a second subregion of the lead frame, and an electrical connection connecting the first subregion to the second subregion, wherein the first subregion is laterally spaced from the second subregion by an intermediate region, wherein the lead frame has at least one subsection, which is located at least in places in the intermediate region and thus in a lateral direction between the first subregion and the second subregion of the first electrode, wherein the intermediate region is at least partially filled by the shaped body or directly adjoins the shaped body, the electrical connection being embedded in the shaped body, and wherein the subsection of the lead frame is neither a subregion of the first electrode nor a subregion of the second electrode.

Embodiments of the present disclosure relate to a semiconductor package, a method of forming semiconductor package and a power module. For example, there is provided a semiconductor package. The semiconductor package may comprise a chip level having a first side and a second side opposite to the first side, wherein the chip level comprises a plurality of power transistors and each power transistor is provided with a source and a gate at the first side. Besides, the semiconductor package may also comprise a first conductive level positioned on the first side and comprising a gate connection portion electrically connected with the gate and a source connection portion electrically connected with the source. The semiconductor package further comprises a second conductive level comprising a gate lead-out portion electrically connected with the gate connection portion and a source lead-out portion electrically connected with the source connection portion, wherein the first conductive level is positioned between the second conductive level and the chip level. Embodiments of the present disclosure may enhance the working performance of the product by improving consistency of conductive paths from the gate and the source of each power transistor to corresponding points.

A package and electronic device are disclosed. In one example, the electronic device comprises a mounting base, an oblong electric connection element, and a package mounted on the mounting base and comprising a carrier, electronic components mounted on the carrier, and an encapsulant at least partially encapsulating the carrier and the electronic components. A clip is connected to upper main surfaces of the electronic components. The encapsulant partially encapsulates the clip so that an exposed surface of the clip is directly electrically connected with the oblong electric connection element extending along the mounting base.

Implementations of a leadframe for a semiconductor package may include a half-etched gate lead directly coupled to a gate tie bar; a half-etched source lead directly coupled to a source tie bar; and a die flag directly coupled to at least two die flag tie bars. The gate tie bar and the source tie bar may be configured to enable electroplating of a flank of the half-etched gate lead and the half-etched source lead.

A substrate assembly may include a power substrate, a chip, a clip, and a trimetal. The power substrate has a first direct copper bonded (DCB) surface connected to a ceramic tile. The chip is soldered onto the first DCB surface. The clip is attached to the power substrate and has a foot at one end and a recessed area at the other, opposite end. The foot is connected to the power substrate. The trimetal has a base, a trapezoid structure, and a clip portion. The base is soldered to the chip. The trapezoid structure is located above the base. The clip portion is located above the trapezoid structure and includes a projecting area. The recessed area of the clip fits into the projecting area of the trimetal.

A method of manufacturing a semiconductor device includes: forming a primary side electrode on a substrate; forming an insulating layer on the substrate and the primary side electrode; forming a secondary side electrode facing the primary side electrode with the insulating layer in between and magnetically or capacitively connected to the primary side electrode on the insulating layer; forming an opening part at the insulating layer by etching to expose part of the primary side electrode; and bonding wiring to the primary side electrode exposed through the insulating layer at the opening part, wherein at least one step is formed on a sidewall of the opening part by performing the etching in a plurality of processes.

A semiconductor device includes a semiconductor die, and a topside metallization on a first side of the semiconductor die. The topside metallization includes a metal layer on the semiconductor die, the metal layer having a first thickness, and at least two discrete bond pads on the metal layer. The discrete bond pads have a second thickness that is larger than the first thickness. A backside metallization may be formed on the back side of the semiconductor die. The backside metallization includes a metal layer having a first portion having a first thickness and a second portion having a second thickness that is smaller than the first thickness.