Packaging solutions for devices and systems comprising lateral GaN power transistors are disclosed, including components of a packaging assembly, a semiconductor device structure, and a method of fabrication thereof. In the packaging assembly, a GaN die, comprising one or more lateral GaN power transistors, is sandwiched between first and second leadframe layers, and interconnected using low inductance interconnections, without wirebonding. For thermal dissipation, the dual leadframe package assembly can be configured for either front-side or back-side cooling. Preferred embodiments facilitate alignment and registration of high current/low inductance interconnects for lateral GaN devices, in which contact areas or pads for source, drain and gate contacts are provided on the front-side of the GaN die. By eliminating wirebonding, and using low inductance interconnections with high electrical and thermal conductivity, PQFN technology can be adapted for packaging GaN die comprising one or more lateral GaN power transistors.

In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and a drain that are located on a first surface of the second die and the source that is located on a second surface of the second die that is opposite the first surface.

In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and a drain that are located on a first surface of the second die and the source that is located on a second surface of the second die that is opposite the first surface.

An integrated circuit package is provided, including: a die having circuitry with one or more bond pads on a first surface of the die; a conductive supporting structure allowing connection to the die, the conductive supporting structure including a slot; and a passive component inserted into the slot of the conductive support structure, and a first terminal of the passive component is electrically connected to the conductive supporting structure and the circuitry of the die.

A fingerprint sensor package includes: a first substrate including a core insulating layer including a first surface and a second surface and a through-hole, a first bonding pad on the second surface, and an external connection pad between an edge of the second surface and the first bonding pad; a second substrate in the through-hole and including a third surface and a fourth surface, and including first sensing patterns on the third surface, spaced apart in a first direction, and extending in a second direction, second sensing patterns spaced apart from each other in the second direction and extending in the first direction, and a second bonding pad on the fourth surface; a conductive support electrically connecting the first bonding pad and the second bonding pad and supporting the first substrate and the second substrate; a controller chip on the second substrate; and a molding layer on the second surface.

A semiconductor device including a lead frame, a die attached to the lead frame using a first solder, and a clip attached to the die using a second solder is provided. The clip includes a notch arranged for a check of the excess of the second solder.

The semiconductor device includes a semiconductor element, a substrate supporting the semiconductor element, a sealing resin covering the semiconductor element and a part of the substrate, and a heat dissipation member. The substrate includes an obverse surface facing a first side in a thickness direction, and a reverse surface facing a second side in the thickness direction and exposed from the sealing resin. The semiconductor element is mounted on the obverse surface. The heat dissipation member is disposed on the substrate on the second side in the thickness direction. The heat dissipation member includes first bases located on the first side in the thickness direction, and first upright portions extending from the first bases to the second side in the thickness direction. The substrate includes first recesses recessed from the reverse surface to the first side in the thickness direction. The first bases are housed in the first recesses.

According to one embodiment, a semiconductor device includes a lead frame, a semiconductor chip, a lead terminal and a package. The package includes an upper surface, a lower surface, and first and second side surfaces between the upper surface and the lower surface. The first side surface has a first surface, a second surface and a third surface. The first surface is continuous with the upper surface and is provided in an oblique direction with respect to the upper surface. The second surface is continuous with the first surface and is provided in a direction parallel to the upper surface. The third surface is continuous with the second surface and is provided in a direction orthogonal to the upper surface. The lead terminal protrudes from the first side surface and does not protrude from the second side surface.