In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and the source that are located on a first surface of the second die and a drain that is located on a second surface of the second die that is opposite the first surface.

An embodiment related to a package is disclosed. The package includes a component mounted to a die attach region on a package substrate. A passive component with first and second passive component terminals is vertically attached to the package substrate. An encapsulant is disposed over the package substrate to encapsulate the package. In one embodiment, an external component is stacked above the encapsulant and is electrically coupled to the encapsulated package.

Provided is a semiconductor package. The semiconductor package includes: a first die that is a monolithic type die, a driver circuit and a low-side output power device formed in the first die; a second die disposed above the first die, the second die comprising a high-side output power device; and a first connection unit disposed between the first die and the second die.

Provided is a semiconductor package. The semiconductor package includes: a first die that is a monolithic type die, a driver circuit and a low-side output power device formed in the first die; a second die disposed above the first die, the second die comprising a high-side output power device; and a first connection unit disposed between the first die and the second die.

Packaging solutions for large area, GaN die comprising one or more lateral GaN power transistor devices and systems are disclosed. Packaging assemblies comprise an interposer sub-assembly comprising the lateral GaN die and a leadframe. The GaN die is electrically connected to the leadframe using bump or post interconnections, silver sintering, or other low inductance interconnections. Then, attachment of the GaN die to the substrate and the electrical connections of the leadframe to contacts on the substrate are made in a single process step. The sub-assembly may be mounted in a standard power module, or alternatively on a substrate, such as a printed circuit board. For high current applications, the sub-assembly also comprises a ceramic substrate for heat dissipation. This packaging scheme provides interconnections with lower inductance and higher current capacity, simplifies fabrication, and enables improved thermal matching of components, compared with conventional wirebonded power modules.

Packaging solutions for devices and systems comprising lateral GaN power transistors are disclosed, including components of a packaging assembly, a semiconductor device structure, and a method of fabrication thereof. In the packaging assembly, a GaN die, comprising one or more lateral GaN power transistors, is sandwiched between first and second leadframe layers, and interconnected using low inductance interconnections, without wirebonding. For thermal dissipation, the dual leadframe package assembly can be configured for either front-side or back-side cooling. Preferred embodiments facilitate alignment and registration of high current/low inductance interconnects for lateral GaN devices, in which contact areas or pads for source, drain and gate contacts are provided on the front-side of the GaN die. By eliminating wirebonding, and using low inductance interconnections with high electrical and thermal conductivity, PQFN technology can be adapted for packaging GaN die comprising one or more lateral GaN power transistors.

In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and a drain that are located on a first surface of the second die and the source that is located on a second surface of the second die that is opposite the first surface.

A semiconductor device has a leadframe and a first electrical component including a first surface disposed on the leadframe. A first clip bond is disposed over a second surface of the first electrical component. The first clip bond extends vertically through the semiconductor device. The first clip bond has a vertical member, horizontal member connected to the vertical member, die contact integrated with the horizontal member, and clip foot extending from the vertical member. A second electrical component has a first surface disposed on the first clip bond. A second clip bond is disposed over a second surface of the second electrical component opposite the first surface of the second electrical component. An encapsulant is deposited around the first electrical component and first clip bond. A second electrical component is disposed over the encapsulant. The clip foot is exposed from the encapsulant.

A semiconductor package and a method of manufacturing the same are provided, in which a height and a one-dimensional area of the semiconductor package may be reduced. The semiconductor package includes a package substrate, a chip stack structure including at least two semiconductor chips aligned with one another and stacked on the package substrate in a vertical direction, each of the at least two semiconductor chips including chip pads exposed at a side surface thereof, an anisotropic conductive film (ACF) covering a side surface of the chip stack structure, and a conductive pattern film covering the ACF and including a conductive pattern connecting the chip pads to a substrate pad of the package substrate.

A power module using electrical insulation film to conduct heat is provided. The power module comprises an electrical insulation film, a heat sink, at least one base metal layer, at least one first semiconductor device, and a sealant. The electrical insulation film is made of an elastic material, and the electrical insulation film is formed on an upper surface of the heat sink. The base metal layer is formed on an upper surface of the electrical insulation film. The first semiconductor device is disposed on the base metal layer. The sealant is disposed on the heat sink. The electrical insulation film is placed on the heat sink for replacing the traditional ceramic substrate, thereby reducing the number of structural layers in the power module.