Provided is a thermally conductive film-like adhesive capable of sufficiently advancing a curing reaction under milder conditions, capable of effectively suppressing residual voids between the adhesive and a wiring board in a semiconductor package to be obtained when used as a die attach film, and capable of obtaining a semiconductor package excellent in heat releasing property inside the package. In addition, provided are a semiconductor package using the thermally conductive film-like adhesive and a method of producing the same.

There is provided a bonding wire for a semiconductor device including a coating layer having Pd as a main component on a surface of a Cu alloy core material and a skin alloy layer containing Au and Pd on a surface of the coating layer, the bonding wire further improving 2nd bondability on a Pd-plated lead frame and achieving excellent ball bondability even in a high-humidity heating condition. The bonding wire for a semiconductor device including the coating layer having Pd as a main component on the surface of the Cu alloy core material and the skin alloy layer containing Au and Pd on the surface of the coating layer has a Cu concentration of 1 to 10 at % at an outermost surface thereof and has the core material containing either or both of Pd and Pt in a total amount of 0.1 to 3.0% by mass, thereby achieving improvement in the 2nd bondability and excellent ball bondability in the high-humidity heating condition. Furthermore, a maximum concentration of Au in the skin alloy layer is preferably 15 at % to 75 at %.

In at least one embodiment, the power semiconductor device (1) comprises: at least one support (2), at least one power semiconductor chip (24) is arranged on a support top side (20), a heat sink (3) having a heat sink top side (30), the at least one support (2) is arranged on the heat sink top side (30), and a mold body (4) of an electric insulating material in direct contact with the at least one support (2) and the heat sink (3),
wherein the mold body (4) fixes and presses the at least one support (2) onto the heat sink (3).

A method of manufacturing a pre-mold substrate includes preparing an electrically conductive substrate, forming a groove on one surface of the substrate, arranging a resin to cover one surface of the substrate and the groove, removing a portion of the resin so that at least a portion of one surface of the substrate protrudes higher than a surface of the resin covering the groove, and forming a circuit pattern on another surface of the substrate.

A wiring body disposed above a substrate including a conductor includes: a via electrode provided in a via hole formed in an insulating layer above the substrate and connected to the conductor through the via hole; and wiring provided above the substrate with the insulating layer interposed therebetween. The material or structure of a lower layer in the via electrode and the material or structure of a lower layer in the wiring are different.

A power semiconductor device includes a semiconductor substrate. A signal routing structure is disposed above the semiconductor substrate. The signal routing structure comprises a specific metal. A solderable power pad forms a power terminal of the power semiconductor device. The solderable power pad comprises the specific metal. An electrically insulating dielectric passivation layer is disposed between the solderable power pad and the signal routing structure.

The present disclosure relates to semiconductors technologies and provides a chip package and a manufacturing method of the chip package. The chip package includes: an interposer; a plurality of semiconductor chips optically connected to the interposer, wherein the plurality of semiconductor chips includes at least four semiconductor chips; and an optical interconnect chip optically connected to the interpose. Each of the plurality of semiconductor chips is configured to be optically connected to the optical interconnect chip via the interposer, to realize optical signal communication between any two of the plurality of semiconductor chips.

A power semiconductor chip having: a semiconductor component body; a multilayer metallization arranged on the semiconductor component body; and a nickel layer arranged over the semiconductor component body. The invention further relates to a method for producing a power semiconductor chip and to a power semiconductor device. The invention provides a power semiconductor chip which has a metallization to which a copper wire, provided without a thick metallic coating, can be reliably bonded without damage to the power semiconductor chip during bonding.

A power semiconductor chip having: a semiconductor component body; a multilayer metallization arranged on the semiconductor component body; and a nickel layer arranged over the semiconductor component body. The invention further relates to a method for producing a power semiconductor chip and to a power semiconductor device. The invention provides a power semiconductor chip which has a metallization to which a copper wire, provided without a thick metallic coating, can be reliably bonded without damage to the power semiconductor chip during bonding.

The present invention has as its object the provision of a bonding wire for semiconductor devices mainly comprised of Ag, in which bonding wire for semiconductor devices, the bond reliability demanded for high density mounting is secured and simultaneously a sufficient, stable bond strength is realized at a ball bond, no neck damage occurs even in a low loop, the leaning characteristic is excellent, and the FAB shape is excellent. To solve this problem, the bonding wire for semiconductor devices according to the present invention contains one or more of Be, B, P, Ca, Y, La, and Ce in a total of 0.031 at % to obtain a 0.180 at %, further contains one or more of In, Ga, and Cd in a total of 0.05 at % to 5.00 at %, and has a balance of Ag and unavoidable impurities. Due to this, it is possible to obtain a bonding wire for semiconductor devices sufficiently forming an intermetallic compound layer at a ball bond interface to secure the bond strength of the ball bond, not causing neck damage even in a low loop, having a good leaning characteristic, and having a good FAB shape.