A MEMS package including a fixed frame, a moveable platform and elastic restoring members is provided. The moveable platform is moved with respect to the fixed frame. The elastic restoring members are connected between the fixed frame and the moveable platform, and used to restore the moved moveable platform to an original position.

A MEMS package including a fixed frame, a moveable platform and elastic restoring members is provided. The moveable platform is moved with respect to the fixed frame. The elastic restoring members are connected between the fixed frame and the moveable platform, and used to restore the moved moveable platform to an original position.

Memory devices are disclosed. A memory device may include a command and address (CA) interface region including a first CA input circuit configured to generate a first CA output AND a second CA input circuit configured to generate a second CA output. The first CA input circuit and the second CA input circuit are arranged in a mirror relationship. The CA interface region further includes a swap circuit configured to select one of the first CA output and the second CA output for a first internal CA signal and select the other of the first CA output and the second CA output for a second internal CA signal. Memory systems and systems are also disclosed.

Memory devices are disclosed. A memory device may include a command and address (CA) interface region including a first CA input circuit configured to generate a first CA output AND a second CA input circuit configured to generate a second CA output. The first CA input circuit and the second CA input circuit are arranged in a mirror relationship. The CA interface region further includes a swap circuit configured to select one of the first CA output and the second CA output for a first internal CA signal and select the other of the first CA output and the second CA output for a second internal CA signal. Memory systems and systems are also disclosed.

A dual-side cooling (DSC) semiconductor package includes a first metal-insulator-metal (MIM) substrate having a first insulator layer, first metallic layer, and second metallic layer. A second MIM substrate includes a second insulator layer, third metallic layer, and fourth metallic layer. The third metallic layer includes a first portion having a first contact area and a second portion, electrically isolated from the first portion, having a second contact area. A semiconductor die is coupled with the second metallic layer and is directly coupled with the third metallic layer through one or more solders, sintered layers, electrically conductive tapes, solderable top metal (STM) layers, and/or under bump metal (UBM) layers. The first contact area is electrically coupled with a first electrical contact of the die and the second contact area is electrically coupled with a second electrical contact of the die. The first and fourth metallic layers are exposed through an encapsulant.

A dual-side cooling (DSC) semiconductor package includes a first metal-insulator-metal (MIM) substrate having a first insulator layer, first metallic layer, and second metallic layer. A second MIM substrate includes a second insulator layer, third metallic layer, and fourth metallic layer. The third metallic layer includes a first portion having a first contact area and a second portion, electrically isolated from the first portion, having a second contact area. A semiconductor die is coupled with the second metallic layer and is directly coupled with the third metallic layer through one or more solders, sintered layers, electrically conductive tapes, solderable top metal (STM) layers, and/or under bump metal (UBM) layers. The first contact area is electrically coupled with a first electrical contact of the die and the second contact area is electrically coupled with a second electrical contact of the die. The first and fourth metallic layers are exposed through an encapsulant.

In an optical receiver circuit which suppresses an unnecessary increase in impedance and occurrences of resonance and radiation noise and which produces preferable high-frequency transmission characteristics, a PD submount mounted with a PD chip and a chip capacitor and a TIA carrier mounted with a TIA chip are electrically connected to each other by a bonding wire. The chip includes an anode electrode pad and a cathode electrode pad, anode electrode-side ground pads are formed at positions that sandwich the pad, and cathode electrode-side ground pads are formed at positions that sandwich the pad. A wire electrically connects the pad and a signal pad for input of the chip to each other, a wire electrically connects the pad and the capacitor to each other, and a wire electrically connects the pads and the pads to each other.

In an optical receiver circuit which suppresses an unnecessary increase in impedance and occurrences of resonance and radiation noise and which produces preferable high-frequency transmission characteristics, a PD submount mounted with a PD chip and a chip capacitor and a TIA carrier mounted with a TIA chip are electrically connected to each other by a bonding wire. The chip includes an anode electrode pad and a cathode electrode pad, anode electrode-side ground pads are formed at positions that sandwich the pad, and cathode electrode-side ground pads are formed at positions that sandwich the pad. A wire electrically connects the pad and a signal pad for input of the chip to each other, a wire electrically connects the pad and the capacitor to each other, and a wire electrically connects the pads and the pads to each other.

A semiconductor chip is arranged on a first surface of a die pad in a substrate (leadframe) including an array of electrically conductive leads. An encapsulation of laser direct structuring (LDS) material encapsulates the substrate and the semiconductor chip. The encapsulation has a first surface, a second surface opposed to the first surface and a peripheral surface. The array of electrically conductive leads protrude from the peripheral surface with areas of the second surface of the encapsulation arranged between adjacent leads. LDS structured areas of the second surface located between adjacent leads in the array of electrically conductive leads provide a further array of electrically conductive leads exposed at the second surface. First and second electrically conductive vias extending through the encapsulation material as well as electrically conductive lines over the encapsulation material provide an electrical bonding pattern between the semiconductor chip and selected ones of the leads.

A semiconductor chip is arranged on a first surface of a die pad in a substrate (leadframe) including an array of electrically conductive leads. An encapsulation of laser direct structuring (LDS) material encapsulates the substrate and the semiconductor chip. The encapsulation has a first surface, a second surface opposed to the first surface and a peripheral surface. The array of electrically conductive leads protrude from the peripheral surface with areas of the second surface of the encapsulation arranged between adjacent leads. LDS structured areas of the second surface located between adjacent leads in the array of electrically conductive leads provide a further array of electrically conductive leads exposed at the second surface. First and second electrically conductive vias extending through the encapsulation material as well as electrically conductive lines over the encapsulation material provide an electrical bonding pattern between the semiconductor chip and selected ones of the leads.