A system in package and method for making a system in package. A plurality of passive devices are coupled to an interposer. A molding compound envelopes the plurality of passive devices and defines a platform having a substantially planar surface. The interposer is coupled to a substrate. A plurality of integrated circuit dies are coupled in a stack to the planar surface.

A semiconductor arrangement includes a controllable semiconductor element having an active region, and bonding wires arranged in parallel to each other in a first horizontal direction. The active region has a first length in the first horizontal direction and a first width in a second horizontal direction perpendicular to the first horizontal direction. Each bonding wire is electrically and mechanically coupled to the controllable semiconductor element by a first number of bond connections arranged above the active region. A first bond connection of each bonding wire is arranged at a first distance from a first edge of the active region. A second bond connection of each bonding wire is arranged at a second distance from a second edge of the active region opposite the first edge. The first and second distances are both less than the first length divided by twice the first number of bond connections.

A current sensor device may include a routable molded lead frame that includes a molded substrate. The current sensor device may include a conductor and a semiconductor chip mounted to the molded substrate. The semiconductor chip may include a magnetic field sensor that is galvanically isolated from the conductor by the molded substrate and is configured to sense a magnetic field created by current flowing through the conductor. The current sensor device may include one or more leads configured to output a signal generated by the semiconductor chip. The one or more leads may be galvanically isolated from the conductor by the molded substrate.

A bonding wire for connecting a first pad to a second pad is provided. The bonding wire includes a ball part bonded to the first pad, a neck part formed on the ball part, and a wire part extending from the neck part to the second pad. Less than an entire portion of a top surface of the neck part is covered by the wire part, and the wire part is in contact with the neck part, the ball part, and the first pad.

A semiconductor package includes a package substrate which includes a substrate base and a plurality of wiring patterns, a lower semiconductor chip, and an upper semiconductor chip. The substrate base includes a chip-accommodating cavity and the plurality of wiring patterns include a plurality of bottom wiring patterns on a bottom surface of the substrate base and a plurality of top wiring patterns on a top surface of the substrate base. The lower semiconductor chip is disposed in the chip-accommodating cavity and is connected to the plurality of bottom wiring patterns through a plurality of lower bonding wires. The upper semiconductor chip includes a first portion which is attached to the lower semiconductor chip and a second portion which overhangs the lower semiconductor chip.

A semiconductor apparatus includes: a metal plate; a semiconductor device mounted on the metal plate; an external terminal electrically connected to the semiconductor device or the metal plate; a metal wire wire-bonded to the semiconductor device, the metal plate or the external terminal; and a package covering and resin-sealing the semiconductor device, the metal plate and the metal wire, wherein the metal wire is bonded to a top-layer electrode of the semiconductor device at a first bond and a second bond, and the metal wire includes a low loop that is positioned between the first bond and the second bond, is adjacent to at least one of the first bond and the second bond and is not in contact with the top-layer electrode.

A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.

A semiconductor device includes a shielding wire formed across a semiconductor die and an auxiliary wire supporting the shielding wire, thereby reducing the size of a package while shielding the electromagnetic interference generated from the semiconductor die. In one embodiment, the semiconductor device includes a substrate having at least one circuit device mounted thereon, a semiconductor die spaced apart from the circuit device and mounted on the substrate, a shielding wire spaced apart from the semiconductor die and formed across the semiconductor die, and an auxiliary wire supporting the shielding wire under the shielding wire and formed to be perpendicular to the shielding wire. In another embodiment, a bump structure is used to support the shielding wire. In a further embodiment, an auxiliary wire includes a bump structure portion and wire portion and both the bump structure portion and the wire portion are used to support the shielding wire.

At the time of clamping, excessive stress is applied to bonding parts between substrates and input/output terminals, which may cause the bonding parts to be detached and cause the substrates to be cracked. A lower electrode of a power semiconductor element 11 is connected via a bonding material 13 to a first interconnection layer 12 arranged on a lower surface of the power semiconductor element 11, and an upper electrode 14 of the power semiconductor element 11 is connected via the bonding material 13 to a second interconnection layer 15 arranged on an upper surface. Also, a second main terminal 16 electrically connected to the upper electrode 14 of the power semiconductor element 11 is connected via the bonding material 13 to the second interconnection layer 15 and contacts and is positioned on a third interconnection layer 24 (spacer) arranged to be parallel to the first interconnection layer 12 on the lower surface. An insulating layer 26 is laminated on a surface of each of the first interconnection layer 12 to the third interconnection layer 24 opposite the bonding material 13, and a heat dissipating layer 27 is laminated on the insulating layer 26.

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, amounting layer, switching elements, a moisture-resistant layer and a sealing resin. The substrate has a front surface facing in a thickness direction. The mounting layer is electrically conductive and disposed on the front surface. Each switching element includes an element front surface facing in the same direction in which the front surface faces along the thickness direction, a back surface facing in the opposite direction of the element front surface, and a side surface connected to the element front surface and the back surface. The switching elements are electrically bonded to the mounting layer with their back surfaces facing the front surface. The moisture-resistant layer covers at least one side surface. The sealing resin covers the switching elements and the moisture-resistant layer. The moisture-resistant layer is held in contact with the mounting layer and the side surface so as to be spanned between the mounting layer and the side surface in the thickness direction.