A semiconductor device includes a die pad, a semiconductor chip with a bonding pad being formed, a lead one end of which is located in the vicinity of the semiconductor chip, a coupling wire that connects an electrode and the lead, and a sealing body that seals the semiconductor chip, the coupling wire, a part of the lead, and a part of the die pad. A lower surface of the die pad is exposed from a lower surface of the sealing body, the die pad and the coupling wire are comprised of copper, and a thickness of the semiconductor chip is larger than the sum of a thickness of the die pad and a thickness from an upper surface of the semiconductor chip to an upper surface of the sealing body.

A switched-mode power converter configured to control at least one phase of a polyphase electrical receiver with at least three phases, comprising at least one block of two converter arms, wherein a half-arm of a converter arm comprises: a first set of P?2 switches in series; a second set of P?2 switches in series; and a third set of diodes, arranged between the first set and the second set, comprising M?2 subsets in series, indexed i?[[1; M]], respectively comprising N.sub.i?2 diodes in parallel.

A lead frame includes a die pad having an upper surface and a lower surface, and a curved part disposed outside the die pad in a bottom view, and having one end connected to an outer edge of the die pad. The curved part has a groove that opens toward the lower surface of the die pad, and the curved part is curved toward the upper surface of the die pad at the groove.

An insulation chip includes first and second units bonded to each other. The first unit includes a first semiconductor substrate, a first element insulating layer including a first element front surface facing the second unit and a first element back surface, and first and fourth insulating elements buried in the first element insulating layer at positions spaced apart from the first element front surface. The second unit includes a second element insulating layer having a second element front surface and a second element back surface, and second and third insulating elements buried in the second element insulating layer at positions spaced apart from the second element front surface. When the second unit is bonded to the first unit, the first and second insulating elements are arranged to face each other, and the third and fourth insulating elements are arranged to face each other.

Aspects of the subject disclosure may include, for example, system, comprising a substrate having an interconnect in or on a surface of the substrate, a riser disposed over the surface, the riser being configured with one or more through riser vias for coupling to the interconnect, a device positioned over the surface, the device having one or more conductive contacts residing in a plane of the device, and one or more wire bonds coupling the one or more through riser vias with the one or more conductive contacts thereby enabling connectivity of the interconnect to be raised toward or to the plane of the device such that at least one of the one or more wire bonds has a limited physical length. Other embodiments are disclosed.

Provided is an electronic package, including: a carrier, an electronic component disposed on the carrier, and an antenna structure, wherein the antenna structure has a plurality of spacing members and at least one wire connected among the spacing members. No additional layout area is required to be formed on a surface of the carrier, such that the objective of miniaturization can be achieved.

A multilayer chipset structure is provided. The chips can be arranged in a stacking structure with multilayer circuit board. Each circuit board is formed with wiring opening and chipset opening. The chipset opening can be arranged with at least one chipset, such as a controller. The different openings cause connecting wires can pass therethrough so as to connect different chips or circuit elements on different layer. By this modularized structure, the multilayer package structure can be formed with a complicated structure in one package so as to reduce the packaging cost effectively. The connecting wires pass through the openings so as to reduce the whole path lengths needed. No complicated wiring is needed. All the conducting wires are at an upper side of the chips. In packaging, it only needs to package the upper side.

An electronic device made from the method of providing a donor substrate comprising an array of metallic interconnects, using a laser system to prepare the metallic interconnects, forming shaped metallic interconnects, laser bending the shaped metallic interconnects; and transferring the shaped metallic interconnects onto a receiving substrate or device.

A common-source type package structure is provided in the present invention. In the package structure, an integrated component body is configured a common-source pin region, a first arrangement region and a second arrangement region. The second and first arrangement regions are spaced apart from each other. A first MOSFET die and a second MOSFET are respectively located at the first and second arrangement region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed to the top surface and spaced apart from each other. A common-source connection element is connected to the source electrode pad and the common-source pin region. A gate connection element is connected to the gate electrode pad and a gate pin region of the integrated component body.

An electronic device includes a carrier and a semiconductor chip, wherein the carrier includes a first dielectric layer and a second dielectric layer, a thermal conductivity of the first dielectric layer exceeds a thermal conductivity of the second dielectric layer, the second dielectric layer is arranged on the first dielectric layer and partially covers the first dielectric layer, the semiconductor chip is arranged on the carrier in a mounting area in which the first dielectric layer is not covered by the second dielectric layer, and the carrier includes a solder terminal for electrical contacting arranged on the second dielectric layer.