Apparatus for communication across a capacitively coupled channel are disclosed herein. An example circuit includes a first plate substantially parallel to a substrate, thereby forming a first capacitance intermediate the first plate and the substrate. A second plate is substantially parallel to the substrate and the first plate, the first plate intermediate the substrate and the second plate. A third plate is substantially parallel to the substrate, thereby forming a second capacitance intermediate the third plate and the substrate. A fourth plate is substantially parallel to the substrate and the third plate, the third plate intermediate the substrate and the fourth plate. An inductor is connected to the first plate and the third plate, the inductor to, in combination with the first capacitance and the second capacitance, form an LC amplifier.

A semiconductor device includes a leadframe, a semiconductor chip mounted on the leadframe, and an encapsulation resin covering the leadframe and the semiconductor chip. The leadframe includes a terminal having a pillar shape. The terminal includes a first end surface, a second end surface facing away from the first end surface, and a side surface extending vertically between the first end surface and the second end surface. The side surface is stepped to form a step surface facing away from the second end surface and having an uneven surface part formed therein. A first portion of the terminal extending from the first end surface toward the second end surface and including the step surface is covered with the encapsulation resin. A second portion of the terminal extending from the first portion to the second end surface projects from the encapsulation resin.

Embodiments of a semiconductor packaged device and method of making thereof are provided, the device including a substrate; a first flip chip die mounted to a first major surface of the substrate; a second flip chip die mounted to the first major surface of the substrate, the second flip chip die laterally adjacent to the first flip chip die on the first major surface; and a wire bond formed between a first bond pad on the first flip chip die and a second bond pad on the second flip chip die.

In a microelectronic package, a first wire bond wire is coupled to an upper surface of a substrate. A first bond mass is coupled to another end of the first wire bond wire. A second wire bond wire is coupled to the upper surface. A second bond mass is coupled to another end of the second wire bond wire. The first and second wire bond wires laterally jut out horizontally away from the upper surface of the substrate for at least a distance of approximately 2 to 3 times a diameter of both the first wire bond wire and the second wire bond wire. The first wire bond wire and the second wire bond wire are horizontal for the distance with respect to being co-planar with the upper surface within +/10 degrees.

An object is to provide a technology that reduces the number of components and that is capable of suppressing the cost. A structure including semiconductor elements, a plurality of electrode terminals, and a dam bar for connecting the plurality of electrode terminals is prepared, and a part of the structure including a part of the plurality of electrode terminals and the dam bar is arranged in the terminal hole. Further, the part of the structure is clamped by a movable clamp inside the terminal hole, and at least a portion of the movable clamp is fitted into the terminal hole, and then a resin is injected into an internal space of a pair of molds.

The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure and a dielectric structure. The conductive structure has a first conductive surface and a second conductive surface opposite to the first conductive surface. The dielectric structure covers at least a portion of the conductive structure, and has a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The first conductive surface does not protrude from the first dielectric surface, and the second conductive surface is recessed from the second dielectric surface. The dielectric structure includes, or is formed from, a photo-sensitive resin, and the dielectric structure defines a dielectric opening in the second dielectric surface to expose a portion of the second conductive surface.

A common-source type package structure is provided in the present invention. In the package structure, an integrated component body is configured a common-source pin region, a first arrangement region and a second arrangement region. The second and first arrangement regions are spaced apart from each other. A first MOSFET die and a second MOSFET are respectively located at the first and second arrangement region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed to the top surface and spaced apart from each other. A common-source connection element is connected to the source electrode pad and the common-source pin region. A gate connection element is connected to the gate electrode pad and a gate pin region of the integrated component body.

A common-source type package structure is provided in the present invention. In the package structure, an integrated component body is configured a common-source pin region, a first arrangement region and a second arrangement region. The second and first arrangement regions are spaced apart from each other. A first MOSFET die and a second MOSFET are respectively located at the first and second arrangement region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed to the top surface and spaced apart from each other. A common-source connection element is connected to the source electrode pad and the common-source pin region. A gate connection element is connected to the gate electrode pad and a gate pin region of the integrated component body.

A common-source type package structure is provided in the present invention. In the package structure, an integrated component body is configured a common-source pin region, a first arrangement region and a second arrangement region. The second and first arrangement regions are spaced apart from each other. A first MOSFET die and a second MOSFET are respectively located at the first and second arrangement region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed to the top surface and spaced apart from each other. A common-source connection element is connected to the source electrode pad and the common-source pin region. A gate connection element is connected to the gate electrode pad and a gate pin region of the integrated component body.

A power semiconductor device is provided. The power semiconductor device includes a leadframe, which includes a first chip carrier part and at least one second chip carrier part, which are fitted at a distance from one another and are in each case electrically conductive, at least one first power semiconductor component applied on the first chip carrier part, at least one second power semiconductor component applied on the second chip carrier part, external contacts in the form of external leads, and a capacitor. The capacitor is mounted on two adjacent external leads.