A semiconductor device has a first area in which first and third semiconductor elements are formed, a second area in which second and fourth semiconductor elements are formed, and a third area located between the first and second areas. On the first to fourth semiconductor elements, a multilayer wiring layer including first and second inductors is formed. A through hole penetrating the semiconductor substrate is formed in the third area, and a first element isolation portion protruding from a front surface side of the semiconductor substrate toward a back surface side of the semiconductor substrate is formed in the through hole. Further, on the back surface side of the semiconductor substrate, the semiconductor substrate in the first area is mounted on the first die pad, and the semiconductor substrate in the second area is mounted on the second die pad.

A fan-out wafer level package includes a semiconductor die with a redistribution layer on a sidewall of the semiconductor die. A redistribution layer positioned over the die includes an extended portion that extends along the sidewall. The semiconductor die is encapsulated in a molding compound layer. The molding compound layer is positioned between the extended portion of the redistribution layer and the sidewall of the semiconductor die. Solder contacts, for electrically connecting the semiconductor device to an electronic circuit board, are positioned on the redistribution layer. The solder contacts and the sidewall of the redistribution layer can provide electrical contact on two different locations. Accordingly, the package can be used to improve interconnectivity by providing vertical and horizontal connections.

A semiconductor device includes a first terminal, a second terminal, and a plurality of third terminals on a substrate. Memory chips are stacked on the substrate in an offset manner. Each memory chip has first pads, second pads, and third pads thereon. A first bonding wire is electrically connected to the first terminal and physically connected to a first pad of each memory chip. A second bonding wire is electrically connected to the second terminal and physically connected to a second pad of each memory chip. A third bonding wire electrically connects one third terminal to a third pad on each memory chip. A fourth bonding wire is connected to the first bonding wire at a first pad on a first memory chip of the stack and another first pad on the first memory chip. The fourth bonding wire straddles over the second bonding wire and the third bonding wire.

A pressure sensor device includes a semiconductor die having a die surface that includes a pressure sensitive area; and a bond wire bonded to a first peripheral region of the die surface and extends over the die surface to a second peripheral region of the die surface, wherein the pressure sensitive area is interposed between the second peripheral region and the first peripheral region, wherein the bond wire comprises a crossing portion that overlaps an area of the die surface, and wherein the crossing portion extends over the pressure sensitive area that is interposed between the first and the second peripheral regions.

A method of manufacturing a WBGA package includes providing a carrier having a first surface and a second surface opposite to the first surface of the carrier, wherein the carrier has a through hole extending between the first surface and the second surface of the carrier; disposing an electronic component on the second surface of the carrier, wherein the electronic component includes a first bonding pad and a second bonding pad; and electrically connecting the first bonding pad and the second bonding pad through a first bonding wire.

A semiconductor device includes first and second members. In the first member, a first electronic circuit including a semiconductor element is formed. The second member is joined to an area of part of a first surface of the first member, and includes a second electronic circuit including a semiconductor element formed of a semiconductor material different from that of the semiconductor element of the first electronic circuit. An interlayer insulating film covers the second member and an area of the first surface of the first member to which the second member is not joined. An inter-member connection wire on the interlayer insulating film couples the first and second electronic circuits through an opening in the interlayer insulating film. A shield structure including a first metal pattern disposed on the interlayer insulating film shields a shielded circuit, which is part of the first electronic circuit, in terms of radio frequencies.

Micromachined ultrasonic transducers integrated with complementary metal oxide semiconductor (CMOS) substrates are described, as well as methods of fabricating such devices. Fabrication may involve two separate wafer bonding steps. Wafer bonding may be used to fabricate sealed cavities in a substrate. Wafer bonding may also be used to bond the substrate to another substrate, such as a CMOS wafer. At least the second wafer bonding may be performed at a low temperature.

A device includes a housing unit with an internal volume. The device further includes a sensor coupled to a substrate via an electrical coupling, wherein the sensor is disposed within the internal volume of the housing unit, and wherein the sensor is in communication with an external environment of the housing unit from a side other than a side associated with the substrate. The device also includes a moisture detection unit electrically coupled to the sensor, wherein the moisture detection unit comprises at least two looped wires forming electrodes, and wherein the moisture detection unit is configured to detect presence of a moisture within an interior environment of the housing unit by measuring a capacitance between the electrodes and by detecting a change between the measured capacitance and a capacitance between the electrodes in absence of moisture.

A semiconductor memory device includes first and second memory chips, each including a region of a core circuit, a first area adjacent to a first side of the region in a first direction, a second area adjacent to a second side of the region in a second direction, a third area adjacent to the first area in the first direction and to the second area in the second direction, a first pad in the first area, a second pad in the second area, and third pad in the third area. In each memory chip, a first bonding wire connects the first and third pads. In addition, a second bonding wire connects the second pads of the first and second memory chips. The second memory chip is stacked on the first memory chip to expose the first, second, and third areas of the first memory chip in a third direction.

A semiconductor and a method of fabricating the semiconductor having multiple, interconnected die including: providing a semiconductor substrate having a plurality of disparate die formed within the semiconductor substrate, and a plurality of scribe lines formed between pairs of adjacent die of the plurality of disparate die; and fabricating, by a lithography system, a plurality of inter-die connections that extend between adjacent pair of die of the plurality of die.