In a multi-chip module (MCM), a super chip (110N) is attached to multiple plain chips (110F super and plain chips can be any chips). The super chip is positioned above the wiring board (WB) but below at least some of plain chips (110F). The plain chips overlap the super chip. Further, the plain chips' low speed IOs can be connected to the WB by long direct connections such as bond wires (e.g. BVAs) or solder stacks; such connections can be placed side by side with the super chip. Such connections can be long, so the super chip is not required to be thin. Also, if through-substrate vias (TSVs) are omitted, the manufacturing yield is high and the manufacturing cost is low. Other structures are provided that combine the short and long direct connections to obtain desired physical and electrical properties.

Miniaturization of a semiconductor device is attained. An SOP1 includes: a semiconductor chip; another semiconductor chip; a die pad over which the former semiconductor chip is mounted; another die pad over which the latter semiconductor chip is mounted; a plurality of wires; and a sealing body. In plan view of the SOP1, the former semiconductor chip and the former die pad do not overlap the latter semiconductor chip and the latter die pad. Also, in a horizontal direction in cross sectional view, the former semiconductor chip and the former die pad do not overlap the latter semiconductor chip and the latter die pad.

A method for connecting an integrated circuit (IC) to a printed circuit board (PCB) can include the steps of fixing the IC and the PCB to a dielectric substrate. A single wire bond can be used to bond the IC to the PCB, and a ground plane can be established for the PCB. To minimize inductance losses at high frequency operation, a ground plane defect can be intentionally established by forming at least one opening in the ground plane. The opening can be rectangular when viewed in top plan, although the number of openings formed and opening geometry can be chosen according to the desired operating frequency of the device. The defect can allow for single wire bonding of the IC to the PCB in a manner which allows for high frequency operation without requiring the integration of additional matching network components on the IC and PCB.

A method for connecting an integrated circuit (IC) to a printed circuit board (PCB) can include the steps of fixing the IC and the PCB to a dielectric substrate. A single wire bond can be used to bond the IC to the PCB, and a ground plane can be established for the PCB. To minimize inductance losses at high frequency operation, a ground plane defect can be intentionally established by forming at least one opening in the ground plane. The opening can be rectangular when viewed in top plan, although the number of openings formed and opening geometry can be chosen according to the desired operating frequency of the device. The defect can allow for single wire bonding of the IC to the PCB in a manner which allows for high frequency operation without requiring the integration of additional matching network components on the IC and PCB.

In a multi-chip module (MCM), a super chip (110N) is attached to multiple plain chips (110F super and plain chips can be any chips). The super chip is positioned above the wiring board (WB) but below at least some of plain chips (110F). The plain chips overlap the super chip. Further, the plain chips' low speed IOs can be connected to the WB by long direct connections such as bond wires (e.g. BVAs) or solder stacks; such connections can be placed side by side with the super chip. Such connections can be long, so the super chip is not required to be thin. Also, if through-substrate vias (TSVs) are omitted, the manufacturing yield is high and the manufacturing cost is low. Other structures are provided that combine the short and long direct connections to obtain desired physical and electrical properties.

Miniaturization of a semiconductor device is attained. An SOP1 includes: a semiconductor chip; another semiconductor chip; a die pad over which the former semiconductor chip is mounted; another die pad over which the latter semiconductor chip is mounted; a plurality of wires; and a sealing body. In plan view of the SOP1, the former semiconductor chip and the former die pad do not overlap the latter semiconductor chip and the latter die pad. Also, in a horizontal direction in cross sectional view, the former semiconductor chip and the former die pad do not overlap the latter semiconductor chip and the latter die pad.

A semiconductor package including a package substrate including first and second bonding pads, third bonding pads spaced apart from the first bonding pads, and fourth bonding pads spaced apart from the second bonding pads; a first chip stack including first chips stacked on the package substrate, each first chip including first signal pads and first power/ground pads alternately arranged; a second chip stack including second chips stacked on the first chip stack, each second chip including second signal pads and second power/ground pads alternately arranged; first lower wires that connect the first signal pads to the first bonding pads; second lower wires that connect the first power/ground pads to the second bonding pads; first upper wires that connect the second signal pads of the second chips to the third bonding pads; and second upper wires that connect the second power/ground pads of the second chips to the fourth bonding pads.

In a multi-chip module (MCM), a super chip (110N) is attached to multiple plain chips (110F; super and plain chips can be any chips). The super chip is positioned above the wiring board (WB) but below at least some of plain chips (110F). The plain chips overlap the super chip. Further, the plain chips' low speed IOs can be connected to the WB by long direct connections such as bond wires (e.g. BVAs) or solder stacks; such connections can be placed side by side with the super chip. Such connections can be long, so the super chip is not required to be thin. Also, if through-substrate vias (TSVs) are omitted, the manufacturing yield is high and the manufacturing cost is low. Other structures are provided that combine the short and long direct connections to obtain desired physical and electrical properties.

A module includes a first substrate including first electrodes; a first element bonded to the first substrate, and including second electrodes disposed at a first end of the first element and third electrodes disposed at a second end of the first element opposite from the first end; a second substrate stacked on the first substrate and including a recess; and a second element bonded to a bottom surface of the recess of the second substrate and including fourth electrodes. The first electrodes of the first substrate are electrically connected to the second electrodes at the first end of the first element, and the third electrodes at the second end of the first element are electrically connected to the fourth electrodes of the second element via a through hole formed in the bottom surface of the recess.

A semiconductor module includes: a substrate for mounting a semiconductor element; a frame-shaped housing that surrounds the substrate; a lead terminal that passes through the housing from an inside to an outside of the housing; and a bonding wire configured to electrically connect the semiconductor element to the lead terminal within the housing. The lead terminal has a pad disposed in the housing. The housing has a first surface that is joined to the pad, and a second surface that is joined to the substrate with an adhesive agent, the second surface facing in a direction opposite to the first surface. The inner peripheral surface of the housing has a groove that extends over the entire range from the first surface to the second surface, the groove extending from the substrate toward the pad.